Power Management
2 power reduction modes are implemented in the AT8xC51SND2C: the Idle mode and
the Power-down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 mode detailed in section “X2 Feature”, page 12.
Reset
In order to start-up (cold reset) or to restart (warm reset) properly the microcontroller, an
high level has to be applied on the RST pin. A bad level leads to a wrong initialization of
the internal registers like SFRs, Program Counter… and to unpredictable behavior of
the microcontroller. A proper device reset initializes the AT8xC51SND2C and vectors
the CPU to address 0000h. RST input has a pull-down resistor allowing power-on reset
by simply connecting an external capacitor to VDD as shown in Figure 22. A warm reset
can be applied either directly on the RST pin or indirectly by an internal reset source
such as the watchdog timer. Resistor value and input characteristics are discussed in
the Section “DC Characteristics” of the AT8xC51SND2C datasheet. The status of the
Port pins during reset is detailed in Table 59.
Figure 22. Reset Circuitry and Power-On Reset
VDD
From Internal
Reset Source
P
VDD
To CPU Core
and Peripherals
RST
+
RST
VSS
RST input circuitry
Power-on Reset
Table 59. Pin Conditions in Special Operating Modes
Mode
Port 0
Floating
Data
Port 1
High
Port 2
High
Port 3
High
Port 4
High
Port 5
MMC
Floating
Data
Audio
1
Reset
Idle
High
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Data
Power-down
Data
Data
Note:
1. Refer to section “Audio Output Interface”, page 73.
Cold Reset
2 conditions are required before enabling a CPU start-up:
•
•
V
DD must reach the specified VDD range
The level on X1 input pin must be outside the specification (VIH, VIL)
If one of these 2 conditions are not met, the microcontroller does not start correctly and
can execute an instruction fetch from anywhere in the program space. An active level
applied on the RST pin must be maintained till both of the above conditions are met. A
reset is active when the level VIH1 is reached and when the pulse width covers the
period of time where VDD and the oscillator are not stabilized. 2 parameters have to be
taken into account to determine the reset pulse width:
•
•
V
DD rise time,
Oscillator startup time.
To determine the capacitor value to implement, the highest value of these 2 parameters
has to be chosen. Table 60 gives some capacitor values examples for a minimum RRST
of 50 KΩ and different oscillator startup and VDD rise times.
46
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
