Table 55. IPH0 Register
IPH0 (S:B7h) – Interrupt Priority High Register 0
7
-
6
5
4
3
2
1
0
IPHAUD
IPHMP3
IPHS
IPHT1
IPHX1
IPHT0
IPHX0
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
Audio Interface Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHAUD
IPHMP3
IPHS
MP3 Decoder Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
Serial Port Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
Timer 1 Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHT1
IPHX1
IPHT0
IPHX0
External Interrupt 1 Priority Level MSB
Refer to Table 51 for priority level description.
Timer 0 Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
External Interrupt 0 Priority Level MSB
Refer to Table 51 for priority level description.
Reset Value = X000 0000b
42
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
