AT8xC51SND2C
Table 58. IPL1 Register
IPL1 (S:B2h) – Interrupt Priority Low Register 1
7
-
6
5
-
4
3
-
2
1
0
IPLUSB
IPLKB
IPLSPI
IPLI2C
IPLMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLUSB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLKB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
IPLSPI
IPLI2C
IPLMMC
Two Wire Controller Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
MMC Interrupt Priority Level LSB
Refer to Table 51 for priority level description.
Reset Value = 0000 0000b
45
4341D–MP3–04/05
ATMEL [ ATMEL ]
