AT8xC51SND2C
Table 56. IPH1 Register
IPH1 (S:B3h) – Interrupt Priority High Register 1
7
-
6
5
-
4
3
-
2
1
0
IPHUSB
IPHKB
IPHSPI
IPHI2C
IPHMMC
Bit
Bit
Number
Mnemonic Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is always 0. Do not set this bit.
USB Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHUSB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Keyboard Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHKB
-
Reserved
The value read from this bit is always 0. Do not set this bit.
SPI Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
IPHSPI
IPHI2C
IPHMMC
Two Wire Controller Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
MMC Interrupt Priority Level MSB
Refer to Table 51 for priority level description.
Reset Value = 0000 0000b
43
4341D–MP3–04/05
ATMEL [ ATMEL ]
