AT8xC51SND2C
External Interrupts
INT1:0 Inputs
External interrupts INT0 and INT1 (INTn, n = 0 or 1) pins may each be programmed to
be level-triggered or edge-triggered, dependent upon bits IT0 and IT1 (ITn, n = 0 or 1) in
TCON register as shown in Figure 20. If ITn = 0, INTn is triggered by a low level at the
pin. If ITn = 1, INTn is negative-edge triggered. External interrupts are enabled with bits
EX0 and EX1 (EXn, n = 0 or 1) in IEN0. Events on INTn set the interrupt request flag IEn
in TCON register. If the interrupt is edge-triggered, the request flag is cleared by hard-
ware when vectoring to the interrupt service routine. If the interrupt is level-triggered, the
interrupt service routine must clear the request flag and the interrupt must be deas-
serted before the end of the interrupt service routine.
INT0 and INT1 inputs provide both the capability to exit from Power-down mode on low
level signals as detailed in section “Exiting Power-down Mode”, page 48.
Figure 20. INT1:0 Input Circuitry
0
1
INT0/1
Interrupt
Request
INT0/1
IE0/1
TCON.1/3
EX0/1
IEN0.0/2
IT0/1
TCON.0/2
KIN0 Inputs
External interrupts KIN0 provides the capability to connect a keyboard. For detailed
information on this inputs, refer to section “Keyboard Interface”, page 198.
Input Sampling
External interrupt pins (INT1:0 and KIN0) are sampled once per peripheral cycle (6
peripheral clock periods) (see Figure 21). A level-triggered interrupt pin held low or high
for more than 6 peripheral clock periods (12 oscillator in standard mode or 6 oscillator
clock periods in X2 mode) guarantees detection. Edge-triggered external interrupts
must hold the request pin low for at least 6 peripheral clock periods.
Figure 21. Minimum Pulse Timings
Level-Triggered Interrupt
> 1 Peripheral Cycle
1 cycle
Edge-Triggered Interrupt
> 1 Peripheral Cycle
1 cycle
1 cycle
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4341D–MP3–04/05
ATMEL [ ATMEL ]
