Registers
Table 53. IEN0 Register
IEN0 (S:A8h) – Interrupt Enable Register 0
7
6
5
4
3
2
1
0
EA
EAUD
EMP3
ES
ET1
EX1
ET0
EX0
Bit
Bit
Number
Mnemonic Description
Enable All Interrupt Bit
Set to enable all interrupts.
Clear to disable all interrupts.
7
EA
If EA = 1, each interrupt source is individually enabled or disabled by setting or
clearing its interrupt enable bit.
Audio Interface Interrupt Enable Bit
Set to enable audio interface interrupt.
Clear to disable audio interface interrupt.
6
5
4
3
2
1
0
EAUD
EMP3
ES
MP3 Decoder Interrupt Enable Bit
Set to enable MP3 decoder interrupt.
Clear to disable MP3 decoder interrupt.
Serial Port Interrupt Enable Bit
Set to enable serial port interrupt.
Clear to disable serial port interrupt.
Timer 1 Overflow Interrupt Enable Bit
Set to enable timer 1 overflow interrupt.
Clear to disable timer 1 overflow interrupt.
ET1
External Interrupt 1 Enable bit
Set to enable external interrupt 1.
Clear to disable external interrupt 1.
EX1
ET0
Timer 0 Overflow Interrupt Enable Bit
Set to enable timer 0 overflow interrupt.
Clear to disable timer 0 overflow interrupt.
External Interrupt 0 Enable Bit
Set to enable external interrupt 0.
Clear to disable external interrupt 0.
EX0
Reset Value = 0000 0000b
40
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
