AT8xC51SND2C
Registers
Table 173. AUXCON Register
AUXCON (S:90h) – Auxiliary Control Register
7
6
5
-
4
3
2
1
0
SDA
SCL
AUDCDOUT AUDCDIN AUDCCLK AUDCCS
KIN0
Bit
Bit
Number
Mnemonic
Description
TWI Serial Data
7
6
SDA
SDA is the bidirectional Two Wire data line.
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the
slave peripherals. When TWI controller is in slave mode, SCL receives clock
from the master controller.
SCL
Audio DAC Control
5:1
0
Refer to Audio DAC interface section
KIN0
Keyboard Input Line
Reset Value = 1111 1111b
Table 174. SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
7
6
5
4
3
2
1
0
SSCR2
SSPE
SSSTA
SSSTO
SSI
SSAA
SSCR1
SSCR0
195
4341D–MP3–04/05
ATMEL [ ATMEL ]
