Bit
Bit
Number
Mnemonic Description
Synchronous Serial Control Rate Bit 2
Refer to Table 166 for rate description.
7
6
SSCR2
SSPE
Synchronous Serial Peripheral Enable Bit
Set to enable the controller.
Clear to disable the controller.
Synchronous Serial Start Flag
5
4
3
SSSTA
SSSTO
SSI
Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
Synchronous Serial Stop Flag
Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
Synchronous Serial Interrupt Flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if
SSGC set) is recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Master Transmitter Mode in progress
2
SSAA
This bit has no specific effect when in master transmitter mode.
Slave Receiver Mode in progress
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Slave Transmitter Mode in progress
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
Synchronous Serial Control Rate Bit 1
Refer to Table 166 for rate description.
1
0
SSCR1
SSCR0
Synchronous Serial Control Rate Bit 0
Refer to Table 166 for rate description.
Reset Value = 0000 0000b
196
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
