AT8xC51SND2C
Table 168. Status for Master Receiver Mode
Application Software Response
To SSCON
SSSTO SSI
Status
Code Status of the TWI Bus
SSSTA and TWI Hardware
To/From SSDAT
SSSTA
SSAA Next Action Taken by TWI Hardware
A START condition has Write SLA+R
been transmitted
SLA+R will be transmitted.
08h
X
0
0
X
Write SLA+R
SLA+R will be transmitted.
X
X
0
0
0
0
X
X
A repeated START
condition has been
10h
Write SLA+W
transmitted
SLA+W will be transmitted.
Logic will switch to master transmitter mode.
No SSDAT action
Arbitration lost in
TWI bus will be released and not addressed slave
mode will be entered.
0
1
0
0
0
0
0
0
0
0
0
0
X
X
0
1
38h
40h
SLA+R or NOT ACK
No SSDAT action
bit
A START condition will be transmitted when the bus
becomes free.
No SSDAT action
No SSDAT action
Data Byte will be received and NOT ACK will be
returned.
SLA+R has been
transmitted; ACK has
been received
Data Byte will be received and ACK will be returned.
No SSDAT action
No SSDAT action
Repeated START will be transmitted.
1
0
0
1
0
0
X
X
SLA+R has been
transmitted; NOT ACK
has been received
STOP condition will be transmitted and SSSTO flag
will be reset.
48h
50h
58h
No SSDAT action
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
0
0
1
0
0
0
0
0
X
0
1
Read data Byte
Read data Byte
Data Byte will be received and NOT ACK will be
returned.
Data Byte has been
received; ACK has
been returned
Data Byte will be received and ACK will be returned.
Read data Byte
Read data Byte
Repeated START will be transmitted.
1
0
0
1
0
0
X
X
Data Byte has been
received; NOT ACK
has been returned
STOP condition will be transmitted and SSSTO flag
will be reset.
Read data Byte
STOP condition followed by a START condition will
be transmitted and SSSTO flag will be reset.
1
1
0
X
191
4341D–MP3–04/05
ATMEL [ ATMEL ]
