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83C51SND2C-JL 参数 Datasheet PDF下载

83C51SND2C-JL图片预览
型号: 83C51SND2C-JL
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片闪存微控制器与MP3解码器,支持完整的音频接口 [Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface]
分类和应用: 解码器闪存微控制器
文件页数/大小: 235 页 / 2877 K
品牌: ATMEL [ ATMEL ]
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Table 171. Status for Slave Transmitter Mode  
Application Software Response  
To SSCON  
SSSTO SSI  
Status of the TWI Bus  
and TWI Hardware  
Status  
Code  
SSSTA  
To/From SSDAT  
SSSTA  
SSAA Next Action Taken by TWI Hardware  
Write data Byte  
X
0
0
0
0
0
1
Last data Byte will be transmitted.  
Own SLA+R has been  
received; ACK has  
been returned  
A8h  
B0h  
Write data Byte  
Write data Byte  
X
Data Byte will be transmitted.  
Arbitration lost in  
Last data Byte will be transmitted.  
X
X
0
0
0
0
0
1
SLA+R/W as master;  
own SLA+R has been  
received; ACK has  
been returned  
Write data Byte  
Data Byte will be transmitted.  
Data Byte in SSDAT  
has been transmitted;  
ACK has been  
Write data Byte  
Write data Byte  
Last data Byte will be transmitted.  
Data Byte will be transmitted.  
X
X
0
0
0
0
0
1
B8h  
received  
No SSDAT action  
No SSDAT action  
Switched to the not addressed slave mode; no  
recognition of own SLA or GCA.  
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own  
SLA will be recognized; GCA will be recognized if  
SSGC = logic 1.  
Data Byte in SSDAT  
has been transmitted;  
NOT ACK has been  
received  
No SSDAT action  
No SSDAT action  
Switched to the not addressed slave mode; no  
recognition of own SLA or GCA. A START condition  
will be transmitted when the bus becomes free.  
C0h  
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own  
SLA will be recognized; GCA will be recognized if  
SSGC = logic 1. A START condition will be  
transmitted when the bus becomes free.  
No SSDAT action  
No SSDAT action  
Switched to the not addressed slave mode; no  
recognition of own SLA or GCA.  
0
0
0
0
0
0
0
1
Switched to the not addressed slave mode; own  
SLA will be recognized; GCA will be recognized if  
SSGC = logic 1.  
Last data Byte in  
SSDAT has been  
transmitted  
(SSAA= 0); ACK has  
been received  
No SSDAT action  
No SSDAT action  
Switched to the not addressed slave mode; no  
recognition of own SLA or GCA. A START condition  
will be transmitted when the bus becomes free.  
C8h  
1
1
0
0
0
0
0
1
Switched to the not addressed slave mode; own  
SLA will be recognized; GCA will be recognized if  
SSGC = logic 1. A START condition will be  
transmitted when the bus becomes free.  
Table 172. Status for Miscellaneous States  
Application Software Response  
Status  
To SSCON  
Code Status of the TWI Bus  
SSSTA and TWI Hardware  
To/From SSDAT  
SSSTA  
SSSTO  
SSI  
SSAA Next Action Taken by TWI Hardware  
No relevant state  
No SSDAT action  
Wait or proceed current transfer.  
F8h  
00h  
information available;  
SSI = 0  
No SSCON action  
Bus error due to an  
illegal START or STOP  
condition  
No SSDAT action  
Only the internal hardware is affected, no STOP  
condition is sent on the bus. In all cases, the bus is  
released and SSSTO is reset.  
0
1
0
X
194  
AT8xC51SND2C  
4341D–MP3–04/05  
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