AT8xC51SND2C
Registers
Table 17. CKCON Register
CKCON (S:8Fh) – Clock Control Register
7
6
5
-
4
3
-
2
1
0
TWIX2
WDX2
SIX2
T1X2
T0X2
X2
Bit
Bit
Number
Mnemonic Description
Two-Wire Clock Control Bit
Set to select the oscillator clock divided by 2 as TWI clock input (X2
independent).
7
TWIX2
Clear to select the peripheral clock as TWI clock input (X2 dependent).
Watchdog Clock Control Bit
Set to select the oscillator clock divided by 2 as watchdog clock input (X2
independent).
Clear to select the peripheral clock as watchdog clock input (X2 dependent).
6
5
4
3
2
WDX2
Reserved
-
The values read from this bit is indeterminate. Do not set this bit.
Enhanced UART Clock (Mode 0 and 2) Control Bit
Set to select the oscillator clock divided by 2 as UART clock input (X2
independent).
SIX2
-
Clear to select the peripheral clock as UART clock input (X2 dependent)..
Reserved
The values read from this bit is indeterminate. Do not set this bit.
Timer 1 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 1 clock input (X2
independent).
T1X2
Clear to select the peripheral clock as timer 1 clock input (X2 dependent).
Timer 0 Clock Control Bit
Set to select the oscillator clock divided by 2 as timer 0 clock input (X2
independent).
Clear to select the peripheral clock as timer 0 clock input (X2 dependent).
1
0
T0X2
X2
System Clock Control Bit
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER
FOSC/2).
=
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
Reset Value = 0000 000Xb (AT89C51SND2C) or 0000 0000b (AT83SND2C)
Table 18. PLLCON Register
PLLCON (S:E9h) – PLL Control Register
7
6
5
-
4
-
3
2
-
1
0
R1
R0
PLLRES
PLLEN
PLOCK
Bit
Bit
Number
Mnemonic Description
PLL Least Significant Bits R Divider
2 LSB of the 10-bit R divider.
7 - 6
5 - 4
R1:0
-
Reserved
The values read from these bits are always 0. Do not set these bits.
15
4341D–MP3–04/05
ATMEL [ ATMEL ]
