AT8xC51SND2C
Figure 5. Mode Switching Waveforms
X1
X1 ÷ 2
X2 Bit
Clock
X2 Mode(1)
STD Mode
STD Mode
Note:
1. In order to prevent any incorrect operation while operating in X2 mode, user must be
aware that all peripherals using clock frequency as time reference (timers, etc.) will
have their time reference divided by 2. For example, a free running timer generating
an interrupt every 20 ms will then generate an interrupt every 10 ms.
PLL
PLL Description
The AT8xC51SND2C PLL is used to generate internal high frequency clock (the PLL
Clock) synchronized with an external low-frequency (the Oscillator Clock). The PLL
clock provides the MP3 decoder, the audio interface, and the USB interface clocks.
Figure 6 shows the internal structure of the PLL.
The PFLD block is the Phase Frequency Comparator and Lock Detector. This block
makes the comparison between the reference clock coming from the N divider and the
reverse clock coming from the R divider and generates some pulses on the Up or Down
signal depending on the edge position of the reverse clock. The PLLEN bit in PLLCON
register is used to enable the clock generation. When the PLL is locked, the bit PLOCK
in PLLCON register (see Table 18) is set.
The CHP block is the Charge Pump that generates the voltage reference for the VCO by
injecting or extracting charges from the external filter connected on PFILT pin (see
Figure 7). Value of the filter components are detailed in the Section “DC
Characteristics”.
The VCO block is the Voltage Controlled Oscillator controlled by the voltage Vref pro-
duced by the charge pump. It generates a square wave signal: the PLL clock.
Figure 6. PLL Block Diagram and Symbol
PFILT
CHP
PLLCON.1
PLLEN
N divider
N6:0
Up
OSC
CLOCK
Vref
PLL
Clock
PFLD
VCO
Down
PLOCK
PLLCON.0
R divider
R9:0
PLL
CLOCK
OSCclk × (R + 1)
PLLclk = ----------------------------------------------
N + 1
PLL Clock Symbol
13
4341D–MP3–04/05
ATMEL [ ATMEL ]
