Bit
Bit
Number
Mnemonic Description
PLL Reset Bit
3
2
1
PLLRES Set this bit to reset the PLL.
Clear this bit to free the PLL and allow enabling.
Reserved
-
The value read from this bit is always 0. Do not set this bit.
PLL Enable Bit
PLLEN
Set to enable the PLL.
Clear to disable the PLL.
PLL Lock Indicator
0
PLOCK
Set by hardware when PLL is locked.
Clear by hardware when PLL is unlocked.
Reset Value = 0000 1000b
Table 19. PLLNDIV Register
PLLNDIV (S:EEh) – PLL N Divider Register
7
-
6
5
4
3
2
1
0
N6
N5
N4
N3
N2
N1
N0
Bit
Bit
Number
Mnemonic Description
Reserved
7
-
The value read from this bit is always 0. Do not set this bit.
PLL N Divider
7 - bit N divider.
6 - 0
N6:0
Reset Value = 0000 0000b
Table 20. PLLRDIV Register
PLLRDIV (S:EFh) – PLL R Divider Register
7
6
5
4
3
2
1
0
R9
R8
R7
R6
R5
R4
R3
R2
Bit
Bit
Number
Mnemonic Description
PLL Most Significant Bits R Divider
8 MSB of the 10-bit R divider.
7 - 0
R9:2
Reset Value = 0000 0000b
16
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
