AT8xC51SND2C
Internal Pin Structure
Table 16. Detailed Internal Pin Structure
Circuit(1)
Type
Pins
VDD
Input
TST
VDD
Watchdog Output
P
Input/Output
RST
VSS
VDD
VDD
VDD
2 osc
periods
Latch Output
P1
P2
P3
P3
P4
Input/Output
N
VSS
VDD
P0
P
MCMD
MDAT
Input/Output
ISP
N
PSEN
VSS
VDD
ALE
SCLK
DCLK
P
Output
DOUT
DSEL
MCLK
N
VSS
D+
D-
Input/Output
D+
D-
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to
the Section “DC Characteristics”, page 201.
2. When the Two Wire controller is enabled, P3 transistors are disabled allowing pseudo
open-drain structure.
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4341D–MP3–04/05