Clock Controller
The AT8xC51SND2C clock controller is based on an on-chip oscillator feeding an on-
chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are
generated by this controller.
Oscillator
The AT8xC51SND2C X1 and X2 pins are the input and the output of a single-stage on-
chip inverter (see Figure 3) that can be configured with off-chip components such as a
Pierce oscillator (see Figure 4). Value of capacitors and crystal characteristics are
detailed in the section “DC Characteristics”.
The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU
core, and a clock for the peripherals as shown in Figure 3. These clocks are either
enabled or disabled, depending on the power reduction mode as detailed in the section
“Power Management” on page 46. The peripheral clock is used to generate the Timer 0,
Timer 1, MMC, SPI, and Port sampling clocks.
Figure 3. Oscillator Block Diagram and Symbol
0
1
X1
X2
÷ 2
Peripheral
Clock
CPU Core
Clock
X2
CKCON.0
IDL
PCON.0
PD
PCON.1
Oscillator
Clock
PER
CPU
OSC
CLOCK
CLOCK
CLOCK
Peripheral Clock Symbol
CPU Core Clock Symbol
Oscillator Clock Symbol
Figure 4. Crystal Connection
X1
C1
C2
Q
VSS
X2
X2 Feature
Unlike standard C51 products that require 12 oscillator clock periods per machine cycle,
the AT8xC51SND2C need only 6 oscillator clock periods per machine cycle. This fea-
ture called the “X2 feature” can be enabled using the X2 bit(1) in CKCON (see Table 17)
and allows the AT8xC51SND2C to operate in 6 or 12 oscillator clock periods per
machine cycle. As shown in Figure 3, both CPU and peripheral clocks are affected by
this feature. Figure 5 shows the X2 mode switching waveforms. After reset the standard
mode is activated. In standard mode the CPU and peripheral clock frequency is the
oscillator frequency divided by 2 while in X2 mode, it is the oscillator frequency.
Note:
1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see
Table 23 on page 22). Using the AT89C51SND2C (Flash Version) the system can
boot either in standard or X2 mode depending on the X2B value. Using AT83SND2C
(ROM Version) the system always boots in standard mode. X2B bit can be changed
to X2 mode later by software.
12
AT8xC51SND2C
4341D–MP3–04/05
ATMEL [ ATMEL ]
