Table 11. External Access Signal Description
Signal
Name
Alternate
Function
Type
Description
Address Lines
A15:8
I/O
Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface.
P2.7:0
P0.7:0
Address/Data Lines
Multiplexed lower address and data lines for the external memory or the
IDE interface.
AD7:0
ALE
I/O
O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid
address information is available on lines A7:0. An external latch is used
to demultiplex the address from address/data bus.
-
-
ISP Enable Input (AT89C51SND2C Only)
This signal must be held to GND through a pull-down resistor at the
falling reset to force execution of the internal bootloader.
ISP
I/O
Read Signal
RD
O
O
P3.7
P3.6
Read signal asserted during external data memory read operation.
Write Signal
WR
Write signal asserted during external data memory write operation.
External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH (RD).
EA(1)
I
-
Note:
1. For ROM/Flash/ROMless Dice product versions only.
Table 12. System Signal Description
Signal
Name
Alternate
Function
Type
Description
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is
running resets the device. The Port pins are driven to their reset
conditions when a voltage lower than VIL is applied, whether or not the
oscillator is running.
RST
I
-
This pin has an internal pull-down resistor which allows the device to be
reset by connecting a capacitor between this pin and VDD
.
Asserting RST when the chip is in Idle mode or Power-Down mode
returns the chip to normal operation.
Test Input
TST
I
-
Test mode entry signal. This pin must be set to VDD
.
Table 13. Power Signal Description
Signal
Name
Alternate
Function
Type
Description
Digital Supply Voltage
Connect these pins to +3V supply voltage.
VDD
PWR
-
-
Circuit Ground
Connect these pins to ground.
VSS
GND
8
AT8xC51SND2C
4341D–MP3–04/05