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83C51SND2C-JL 参数 Datasheet PDF下载

83C51SND2C-JL图片预览
型号: 83C51SND2C-JL
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片闪存微控制器与MP3解码器,支持完整的音频接口 [Single-Chip Flash Microcontroller with MP3 Decoder with Full Audio Interface]
分类和应用: 解码器闪存微控制器
文件页数/大小: 235 页 / 2877 K
品牌: ATMEL [ ATMEL ]
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Table 11. External Access Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Address Lines  
A15:8  
I/O  
Upper address lines for the external bus.  
Multiplexed higher address and data lines for the IDE interface.  
P2.7:0  
P0.7:0  
Address/Data Lines  
Multiplexed lower address and data lines for the external memory or the  
IDE interface.  
AD7:0  
ALE  
I/O  
O
Address Latch Enable Output  
ALE signals the start of an external bus cycle and indicates that valid  
address information is available on lines A7:0. An external latch is used  
to demultiplex the address from address/data bus.  
-
-
ISP Enable Input (AT89C51SND2C Only)  
This signal must be held to GND through a pull-down resistor at the  
falling reset to force execution of the internal bootloader.  
ISP  
I/O  
Read Signal  
RD  
O
O
P3.7  
P3.6  
Read signal asserted during external data memory read operation.  
Write Signal  
WR  
Write signal asserted during external data memory write operation.  
External Access Enable: EA must be externally held low to enable the  
device to fetch code from external program memory locations 0000H to  
FFFFH (RD).  
EA(1)  
I
-
Note:  
1. For ROM/Flash/ROMless Dice product versions only.  
Table 12. System Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Reset Input  
Holding this pin high for 64 oscillator periods while the oscillator is  
running resets the device. The Port pins are driven to their reset  
conditions when a voltage lower than VIL is applied, whether or not the  
oscillator is running.  
RST  
I
-
This pin has an internal pull-down resistor which allows the device to be  
reset by connecting a capacitor between this pin and VDD  
.
Asserting RST when the chip is in Idle mode or Power-Down mode  
returns the chip to normal operation.  
Test Input  
TST  
I
-
Test mode entry signal. This pin must be set to VDD  
.
Table 13. Power Signal Description  
Signal  
Name  
Alternate  
Function  
Type  
Description  
Digital Supply Voltage  
Connect these pins to +3V supply voltage.  
VDD  
PWR  
-
-
Circuit Ground  
Connect these pins to ground.  
VSS  
GND  
8
AT8xC51SND2C  
4341D–MP3–04/05  
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