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PA7572 参数 Datasheet PDF下载

PA7572图片预览
型号: PA7572
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程电可擦除逻辑阵列 [Programmable Electrically Erasable Logic Array]
分类和应用:
文件页数/大小: 10 页 / 323 K
品牌: ANACHIP [ ANACHIP CORP ]
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Table 5. A.C. Electrical Characteristics Sequential  
-20/I-20  
Symbol  
Parameter6,1  
Unit  
Min  
8
Max  
Internal set-up to system clock8 - LCC14  
ns  
t
SCI  
(tAL + tSK + tLC - tCK  
Input16 (EXT.) set-up to system clock, - LCC (tIA + tSCI  
System-clock to Array Int. - LCC/IOC/INC14 (tCK +tLC  
)
)
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
t
t
t
t
t
t
t
t
t
t
SCX  
COI  
COX  
HX  
SK  
)
7
System-clock to Output Ext. - LCC (tCOI + tLO  
Input hold time from system clock - LCC  
LCC Input set-up to async. clock13 - LCC  
Clock at LCC or IOC - LCC output  
)
12  
0
1
1
4
0
5
AK  
LCC input hold time from system clock - LCC  
Input set-up to system clock - IOC/INC14 (tSK - tCK  
HK  
SI  
)
Input hold time from system clock - IOC/INC (tSK - tCK  
)
HI  
Array input to IOC PCLK clock  
Input set-up to PCLK clock17 - IOC/INC (tSK-tPK-tIA)  
9
PK  
0
SPI  
HPI  
Input hold from PCLK clock17 - IOC/INC (tPK+tIA-tSK  
Input set-up to system clock - IOC/INC Sum-D  
)
10  
10  
0
ns  
ns  
ns  
(tIA + tAL + tLC + tSK - tCK  
)
t
t
t
SD  
Input hold time from system clock - IOC Sum-D  
HD  
Input set-up to PCLK clock - IOC Sum-D15  
7
SDP  
(tIA + tAL + tLC + tSK - tPK  
)
Input hold time from PCLK clock - IOC Sum-D  
0
ns  
ns  
t
t
t
f
f
f
f
f
t
t
t
t
t
t
t
t
HDP  
CK  
System-clock delay to LCC/IOC/INC  
6
System-clock low or high pulse width  
7
ns  
CW  
Max. system-clock frequency Int/Int 1/(tSCI + tCOI  
)
66.6  
58.8  
50.0  
45.4  
71.4  
1
MHz  
MHz  
MHz  
MHz  
MHz  
ns  
MAX1  
MAX2  
MAX3  
MAX4  
TGL  
PR  
Max. system-clock frequency Ext/Int 1/(tSCX + tCOI  
)
)
Max. system-clock frequency Int/Ext 1/(tSCI + tCOX  
Max. system-clock frequency Ext/Ext 1/(tSCX + tCOX  
)
9
Max. system-clock toggle frequency 1/(tCW + tCW  
LCC presents/reset to LCC output  
)
Input to Global Cell present/reset (tIA + tAL + tPR  
Asynch. preset/reset pulse width  
)
15  
ns  
ST  
8
ns  
AW  
Input to LCC Reg-Type (RT)  
8
1
9
ns  
RT  
LCC Reg-Type to LCC output register change  
ns  
RTV  
RTC  
RW  
Input to Global Cell register-type change (tRT + tRTV  
)
ns  
Asynch. Reg-Type pulse width  
Power-on reset time for registers in clear state2  
10  
ns  
5
µs  
RESET  
Anachip Corp.  
www.anachip.com.tw  
Rev. 1.0 Dec 16, 2004  
8/10