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PA7572 参数 Datasheet PDF下载

PA7572图片预览
型号: PA7572
PDF下载: 下载PDF文件 查看货源
内容描述: 可编程电可擦除逻辑阵列 [Programmable Electrically Erasable Logic Array]
分类和应用:
文件页数/大小: 10 页 / 323 K
品牌: ANACHIP [ ANACHIP CORP ]
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Inside the Logic Array  
The heart of the PEEL™ Array architecture is based on a products functions provided to the logic cells can be used for  
logic array structure similar to that of a PLA (programmable clocks, resets, presets and output enables instead of just  
AND, programmable OR). The logic array implements all simple product-term control.  
logic functions and provides interconnection and control of  
The PEEL™ logic array can also implement logic functions  
the cells. In the PA7572 PEEL™ Array, 62 inputs are  
with many product terms within a single-level delay. For  
available into the array from the I/O cells, inputs cells and  
example a 16-bit comparator needs 32 shared product terms  
input/global-clock pins.  
to implement 16 exclusive-OR functions. The PEEL™ logic  
All inputs provide both true and complement signals, which array easily handles this in a single level delay. Other  
can be programmed to any product term in the array. The PLDs/CPLDs either run out of product-terms or require  
PA7572 PEEL™ Arrays contains 124 product terms. All expanders or additional logic levels that often slow  
product terms (with the exception of certain ones fed to the performance and skew timing.  
global cells) can be programmably connected to any of the  
sum-terms of the logic control cells (four sum-terms per  
Logic Control Cell (LCC)  
logic control cell). Product-terms and sum-terms are also  
Logic Control Cells (LCC) are used to allocate and control the  
routed to the global cells for control purposes. Figure 3  
logic functions created in the logic array. Each LCC has four  
shows a detailed view of the logic array structure.  
primary inputs and three outputs. The inputs to each LCC are  
complete sum-of-product logic functions from the array, which  
can be used to implement combinatorial and sequential logic  
functions, and to control LCC registers and I/O cell output  
enables.  
From  
IO Cells  
(IOC,INC,  
I/CLK)  
From Global Cell  
Preset RegType Reset  
System Clock  
62 Array Inputs  
On/Off  
MUX  
To  
Array  
P
D,T,J  
Q
MUX  
REG  
R
From  
Logic  
K
Control  
Cells  
(LCC)  
A
B
C
D
From  
Array  
To  
Global  
Cells  
125 Product  
Terms  
To  
I/O  
Cell  
MUX  
08-15-004A  
To  
Logic Control  
Cells  
(LCC)  
Figure 4. Logic Control Cell Block Diagram  
As shown in Figure 4, the LCC is made up of three signal  
routing multiplexers and a versatile register with synchronous  
or asynchronous D, T, or JK registers (clocked-SR registers,  
which are a subset of JK, are also possible). See Figure 5.  
EEPROM memory cells are used for programming the  
desired configuration. Four sum-of-product logic functions  
(SUM terms A, B, C and D) are fed into each LCC from the  
logic array. Each SUM term can be selectively used for  
multiple functions as listed below.  
08-15-003A  
100 Sum Terms  
PA7572 Logic Array  
Figure 3. PA7572 Logic Array  
True Product-Term Sharing  
The PEEL™ logic array provides several advantages over  
common PLD logic arrays. First, it allows for true product-  
term sharing, not simply product-term steering, as com-  
monly found in other CPLDs. Product term sharing ensures  
that product-terms are used where they are needed and  
not left unutilized or duplicated. Secondly, the sum-of-  
Anachip Corp.  
www.anachip.com.tw  
Rev. 1.0 Dec 16, 2004  
2/10