Sum-A = D, T, J or Sum-A
Sum A, B or C combinatorial paths. Thus, one LCC output
can be registered, one combinatorial and the third, an output
enable, or an additional buried logic function. The multi-
function PEEL™ Array logic cells are equivalent to two or
three macrocells of other PLDs, which have one output per
cell. They also allow registers to be truly buried from I/O pins
without limiting them to input-only (see Figure 8 & Figure 9).
Sum-B = Preset, K or Sum-B
Sum-C = Reset, Clock, Sum-C
Sum-D = Clock, Output Enable, Sum-D
D Register
Q = D after clocked
P
D
Q
Q
Q
Best for storage, simple counters,
shifters and state machines with
few hold (loop) conditions.
R
From Global Cell
Input Cell Clock
T Register
Q toggles when T = 1
Q holds when T = 0
P
R
T
REG/
Latch
Best for wide binary counters (saves
product terms) and state machines
with many hold (loop) conditions.
Q
To
Array
MUX
Input
JK Register
Q toggles when J/K = 1/1
Q holds when J/K = 0/0
Q = 1
Q = 0
Input
P
R
J
Input Cell (INC)
when J/K = 1/0
when J/K = 0/1
K
Combines features of both D and T
registers.
From Global Cell
08-15-005A
Input Cell Clock
Figure 5. LCC Register Types
REG/
Latch
SUM-A can serve as the D, T, or J input of the register or a
combinatorial path. SUM-B can serve as the K input, or the
preset to the register, or a combinatorial path. SUM-C can
be the clock, the reset to the register, or a combinatorial
path. SUM-D can be the clock to the register, the output
enable for the connected I/O cell, or an internal feedback
node. Note that the sums controlling clocks, resets, presets
and output enables are complete sum-of-product functions,
not just product terms as with most other PLDs. This also
means that any input or I/O pin can be used as a clock or
other control function.
Q
To
MUX
Input
Array
MUX
A,B,C
or
Q
MUX
I/O Pin
From
Logic
Control
Cell
MUX
D
0
1
08-15-006A
Several signals from the global cell are provided primarily
for synchronous (global) register control. The global cell
signals are routed to all LCCs. These signals include a
high-speed clock of positive or negative polarity, global
preset and reset, and a special register-type control that
selectively allows dynamic switching of register type. This
last feature is especially useful for saving product terms
when implementing loadable counters and state machines
by dynamically switching from D-type registers to load and
T-type registers to count (see Figure 9).
I/O Cell (IOC)
Figure 6. Input and I/O Cell Block Diagrams
IOC/INC Register
Q = D after rising edge of clock
holds until next rising edge
D
Q
IOC/INC Latch
Q = L when clock is high
holds value when clock is low
L
Q
Multiple Outputs Per Logic Cell
08-15-007A
An important feature of the logic control cell is its capability
to have multiple output functions per cell, each operating
independently. As shown in Figure 4, two of the three
outputs can select the Q output from the register or the
Figure 7. IOC/INC Register Configurations
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
3/10
ANACHIP [ ANACHIP CORP ]
