Input Cells (INC)
Global Cells
Input cells (INC) are included on dedicated input pins. The The global cells, shown in Figure 10, are used to direct global
block diagram of the INC is shown in Figure 6. Each INC clock signals and/or control terms to the LCCs, IOCs and
consists of a multiplexer and a register/transparent latch, INCs. The global cells allow a clock to be selected from the
which can be clocked from various sources selected by the CLK1 pin, CLK2 pin, or a product term from the logic array
global cell (see Figure 7). The register is rising edge (PCLK). They also provide polarity control for INC and IOC
clocked. The latch is transparent when the clock is high clocks enabling rising or falling clock edges for input
and latched on the clock’s falling edge. The register/ latch registers/latches. Note that each individual LCC clock has its
can also be bypassed for a non-registered input.
own polarity control. The global cell for LCCs includes sum-
of-products control terms for global reset and preset, and a
fast product term control for LCC register-type, used to save
product terms for loadable counters and state machines (see
Figure 11). The PA7572 provides two global cells that divide
the LCC and IOCs into groups, A and B. Half of the LCCs and
IOCs use global cell A, half use global cell B. This means that
two high-speed global clocks can be used among the LCCs.
I/O Cell (IOC)
All PEEL™ Arrays have I/O cells (IOC) as shown above in
Figure 6. Inputs to the IOCs can be fed from any of the
LCCs in the array. Each IOC consists of routing and control
multiplexers, an input register/transparent latch, a three-
state buffer and an output polarity control. The register/
latch can be clocked from a variety of sources determined
by the global cell. It can also be bypassed for a non-
registered input. The PA7572 allows the use of SUM-D as
a feedback to the array when the I/O pin is a dedicated
output. This allows for additional buried registers and logic
paths. (See Figure 8 and Figure 9).
CLK1
CLK2
MUX
INC Clocks
PCLK
Global Cell: INC
Group A & B
MUX
MUX
LCC Clocks
IOC Clocks
CLK1
CLK2
Q
D
PCLK
Input with optional
register/latch
I/O
Reg-Type
LCC Reg-Type
LCC Presets
LCC Resets
Preset
Reset
I/O with
independent
output enable
Global Cell: LCC & IOC
08-15-010A
1
D
Q
A
B
C
D
2
Figure 10. Global Cells
OE
Reg-Type from Global Cell
08-15-008A
Figure 8. LCC & IOC With Two Outputs
Register Type Change Feature
Global Cell can dynamically change user-
selected LCC registers from D to T or from D
to JK. This saves product terms for loadable
counters or state machines. Use as D register
to load, use as T or JK to count. Timing
allows dynamic operation.
P
R
D
Q
Q
D
Buried register or
logic paths
Output
Example:
1
D
Q
A
B
C
D
Product terms for 10 bit loadable binary counter
P
R
T
Q
2
3
D uses 57 product terms (47 count, 10 load)
T uses 30 product terms (10 count, 20 load)
D/T uses 20 product terms (10 count, 10 load)
08-15-009A
08-15-011A
Figure 9. LCC & IOC With Three Outputs
Figure 11. Register Type Change Feature
Anachip Corp.
www.anachip.com.tw
Rev. 1.0 Dec 16, 2004
4/10
ANACHIP [ ANACHIP CORP ]
