AS3525-A/-B C22O22
Data Sheet, Confidential
GPIO data register
Table 29 GPIO data register
Name
Base
Default
GPIO1_DATA
AS3525_GPIO1_BASE
AS3525_GPIO2_BASE
AS3525_GPIO3_BASE
AS3525_GPIO4_BASE
0xC80B0000
0xC80C0000
0xC80D0000
0xC80E0000
GPIO2_DATA
GPIO3_DATA
GPIO4_DATA
GPIO data register
In software control mode (GPIO1_AFSEL,...), values written in this register are
transferred onto the GPOUT pins if the respective pins have been configured as
outputs through the GPIO1_DIR, .. .
So that GPIO bits can be set without affect to other pins in a single write operation, the
address bus is used as a mask on read/write operation. The data register covers 256
locations in the address space. The eight address lines used are PADDR[9:2]. During a
write, only GPIO1_DATA,... bits corresponding to HIGH address bits are updated.
During a read all data bits corresponding to HIGH address bits are read, the other bits
are zero.
Offset: 0x000
A read from this register returns the last bit value written if the respective pins are
configured as output, or it returns the value on the corresponding input GPIN bit when
these are configured as inputs. All bits are cleared by a reset.
Bit
Bit Name
Default
Access
Bit Description
7:0
GPIO data register
00000000 RW
Input data, output data.
GPIO data direction register
Table 30 GPIO data direction register
Name
Base
Default
GPIO1_DIR
GPIO2_DIR
GPIO3_DIR
GPIO4_DIR
AS3525_GPIO1_BASE
AS3525_GPIO2_BASE
AS3525_GPIO3_BASE
AS3525_GPIO4_BASE
0xC80B0000
0xC80C0000
0xC80D0000
0xC80E0000
GPIO data direction register
Offset: 0x400
Bits set to HIGH configure corresponding pin to be an output. Clearing a bit configures
the pin to be input. All bits are cleared by a reset.
Bit
Bit Name
Default
Access
Bit Description
7:0
GPIO data direction
register
00000000 RW
0: pins input
1: pins output
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