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A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS3525-A/-B C22O22  
Data Sheet, Confidential  
GPIO interrupt sense register  
Table 31 GPIO interrupt sense register  
Name  
Base  
Default  
GPIO1_IS  
GPIO2_IS  
GPIO3_IS  
GPIO4_IS  
AS3525_GPIO1_BASE  
AS3525_GPIO2_BASE  
AS3525_GPIO3_BASE  
AS3525_GPIO4_BASE  
0xC80B0000  
0xC80C0000  
0xC80D0000  
0xC80E0000  
GPIO interrupt sense register  
Offset: 0x404  
Bits set to HIGH configure the corresponding pins to detect levels. Clearing a bit  
configures the pin to detect edges. All bits are cleared by a reset.  
Bit  
Bit Name  
Default  
Access  
Bit Description  
7:0  
GPIO interrupt sense 00000000 RW  
register  
0: edge on corresponding pin is detected  
1: level on corresponding pin is detected  
GPIO interrupt both edges register  
Table 32 GPIO interrupt both edges register  
Name  
Base  
Default  
GPIO1_IBE  
GPIO2_IBE  
GPIO3_IBE  
GPIO4_IBE  
AS3525_GPIO1_BASE  
AS3525_GPIO2_BASE  
AS3525_GPIO3_BASE  
AS3525_GPIO4_BASE  
0xC80B0000  
0xC80C0000  
0xC80D0000  
0xC80E0000  
GPIO interrupt both edges register  
When the corresponding bit in GPIO interrupt sense register (GPIO1_IS, …) is set to  
detect edges, bits set to HIGH in GPIO interrupt both edges register (GPIO1_IBE, … )  
configure the corresponding pin to detect both rising and falling edges, regardless of  
the corresponding bit in the GPIO interrupt event register (GPIO1_IEV, …). Clearing a  
bit configures the pin to be controlled by GPIO interrupt event register (GPIO1_IEV,  
…). All bits are cleared by a reset.  
Offset: 0x408  
Bit  
Bit Name  
Default  
Access  
Bit Description  
7:0  
GPIO interrupt event 00000000 RW  
register  
0: on corresponding pin interrupt generation event is controlled  
by GPIO interrupt event register (GPIO1_IEV, …).  
1: both edges on corresponding pin trigger an interrupt.  
Single edge determined by corresponding bit in GPIO interrupt  
event register (GPIO1_IEV, …).  
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.  
www.austriamicrosystems.com Revision 1.13  
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