AS3525-A/-B C22O22
Data Sheet, Confidential
The timer clock enable is generated by a prescale unit. The enable is then used by the counter to create a clock with a timing of one of the
following.
•
•
•
The system clock
The system clock divided by 16, generated by 4 bits of prescale
The system clock divided by 256, generated by a total of 8 bits of prescale
Figure 17 - timer prescaler
7.3.1.2 Interrupt generation
An interrupt is generated when the full 32-bit counter reaches zero, and is only cleared when the TimerXClear location is written to. A register holds
the value until the interrupt is cleared. The most significant carry bit of the counter detects the counter reaching zero.
Interrupts can be masked by writing 0 to the interrupt enable bit in the control register. Both the raw interrupt satus (prior to masking) and the final
interrupt status (after masking) can be read from status registers.
Timer 1 interrupt output is connected to interrupt input line irq1 (VIC input) and Timer 2 interrupt output is connected to interrupt line irq2.
7.3.1.3 Timer Register Descriptions
Table 18 – Timer 1 and 2 registers
Register Name
Timer1Load
Base Address
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
AS3525_TIMER_BASE
Offset
0x00
Note
load value for Timer 1
Timer1Value
0x04
current value for Timer 1
Timer1Control
Timer1IntClr
0x08
Timer 1 control register
0x0C
0x10
Timer 1 interrupt clear
Timer1RIS
Timer 1 raw interrupt status
Timer 1 masked interrupt status
Timer 1 background load value
load value for Timer 2
Timer1MIS
0x14
Timer1BGLoad
Timer2Load
0x18
0x20
Timer2Value
0x24
current value for Timer 2
Timer2Control
Timer2IntClr
0x28
Timer 2 control register
0x2C
0x30
Timer 2 interrupt clear
Timer2RIS
Timer 2 raw interrupt status
Timer 2 masked interrupt status
Timer 2 background load value
Peripheral ID register bits 7:0
Peripheral ID register bits 15:8
Peripheral ID register bits 23:16
Peripheral ID register bits 31:24
Primecell ID register bits 7:0
Primecell ID register bits 15:8
Primecell ID register bits 23:16
Primecell ID register bits 31:24
Timer2MIS
0x34
Timer2BGLoad
Periheral ID register bits 7:0
Periheral ID register bits 15:8
0x38
0xFE0
0xFE4
0xFE8
0xFEC
0xFF0
0xFF4
0xFF8
0xFFC
Periheral ID register bits 23:16 AS3525_TIMER_BASE
Periheral ID register bits 31:24 AS3525_TIMER_BASE
Primecell ID register bits 7:0
AS3525_TIMER_BASE
Primecell ID register bits 15:8 AS3525_TIMER_BASE
Primecell ID register bits 23:16 AS3525_TIMER_BASE
Primecell ID register bits 31:24 AS3525_TIMER_BASE
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