AS3525-A/-B C22O22
Data Sheet, Confidential
7.3 APB Peripheral Block
7.3.1 Timers
The Dual Input Timers module is an APB slave that provides access to two interrupt-generating, programmable 32-bit free-running decrementing
counters (FRCs). The system clock (PCLK) is used to control the programmable registers, and the second clock input is used to drive the counter,
enabling the counters to run from a much slower clock than the system clock. This input clock of the counters (TIMCLK) is connected to a clock
derived (divided by 16) from the main clock (clk_main) signal. That clock clk_main is always running and is coming from the internal or external
oscillator (set by clk_sel pad).
7.3.1.1 Timer modes
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Free-running mode: the counter wraps after zero and continues at the maximum value. This is the default mode.
Periodic mode: reload of original value after wrapping past zero.
One-shot mode - interrupt is generated once, counter halts after reaching zero
Figure 16 Timer Block Diagram
Each timer has an identical set of registers shown in table Table 18. The operation of each timer is identical. The timer is loaded by writing to the
load register and, if enabled, counts down to zero. When a counter is already running, writing to the load register will cause the counter to
immediately restart at the new value. Writing to the background load value has no effect on the current count. The counter continues to decrement
to zero, and then recommences from the new load value (if in periodic mode, and one shot mode is not selected).
When zero is reached, an interrupt is generated. The interrupt can be cleared by writing to the clear register. If One Shot Mode is selected, the
counter halts on reaching zero One Shot Mode is deselected, or a new load value is written. Otherwise, after reaching a zero count, if the timer is
operating in free-running mode it continues to decrement from its maximum value. If periodic timer mode is selected, the timer reloads the count
value from the load register and continues to decrement. In this mode the counter effectively generates a periodic interrupt. The mode is selected
by a bit in the timer control register. At any point, the current counter value can be read from the value register. The counter is enabled by a bit in
the control register. At reset, the counter is disabled, the interrupt is cleared, and the load register is set to zero. The mode and prescale values are
set to free-running, and clock divide of 1 respectively.
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