AS3525-A/-B C22O22
Data Sheet, Confidential
Raw Interrupt status register, Timer1RIS, Timer2RIS
This register indicates the raw interrupt status from the counter. This value is ANDed with the timer interrupt enable bit from the control register to
create the masked interrupt, which is passed to the interrupt output pin.
Table 20 raw interrupt status register
Name
Base
Default
Timer1RIS, Timer2RIS
AS3525_TIMER_BASE
Timer raw interrupt status register
Offset: 0x10, 0x30
Contains control bits of the PLLA register.
Bit
Bit Name
Default
Access
Bit Description
0
Raw Timer Interrupt
R
Raw interrupt status from the counter
Interrupt status register, TIMERXMIS
This register indicates the masked interrupt status from the counter. This value is the logical AND of the raw interrupt status with the timer interrupt
enable bit from the control register, and is the same value which is passed to the interrupt output pin.
Table 21 interrupt status register
Name
Base
Default
Timer1MIS, Timer2MIS
AS3525_TIMER_BASE
Timer raw interrupt status register
Offset: 0x10, 0x30
Contains control bits of the PLLA register.
Bit
Bit Name
Default
Access
Bit Description
0
Raw Timer Interrupt
R
Raw interrupt status from the counter
Background load register, TimerXBGLoad
This is a 32 bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when periodic
mode is enabled, and the current count reaches zero.
This register privides an alternative method of accessing the TimerXLoad register. The difference is that writes to TimerXBGLoad will not cause the
counter immediately to restart from the new value.
Reading from this register returns the same value returned from TimerXLoad.
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