AS3525-A/-B C22O22
Data Sheet, Confidential
Load register, Timer1Load, Timer2Load
This is a 32-bit register containing the value from which the counter is to decrement. This is the value used to reload the counter when periodic
mode is enabled, and the current count reaches zero.
When this register is written to directly, the current count is immediately reset to the new value at the next rising edge of TIMCLK which is enabled
by TIMCLKEN.
The value in this register is also overwritten if the TimerXBGLoad register is written to, but the current count is not immediately affected.
If values are written to both the timerXLoad and TimerXBGLoad registers before an enabled rising edge on TIMCLK, the following occurs:
•
•
On the next enabled TIMCLK edge the value written to the TimerXLoad value replaces the current count value
Following this, eacht time the counter reaches zero, the current count value is reset to the value written to TimerXBGLoad.
Reading from the TimerXLoad register at any time after the two writes have occurred will retrieve the value written to TimerXBGLoad. That is, the
value read from TimerXLoad is always the value which will take effect for periodic mode after the next time the counter reaches zero.
Current value register, Timer1Value, Timer2Value
This register gives the current value of the decrementing counter.
Timer control register
Table 19 Timer control register
Name
Base
Default
0x20
Timer1Control, Timer2Control
AS3525_TIMER_BASE
Timer Control Register
Contains control bits of the PLLA register.
Offset: 0x08, 0x28
Bit
Bit Name
Timer Enable
Default
Access
Bit Description
7
0
0
1
R/W
Enable bit:
0: timer disabled (default)
1: timer enabled
Mode bit
0: timer is in free-running mode (default)
1: timer is in periodic mode
6
5
Timer Mode
R/W
R/W
Interrupt Enable
Interrupt enable bit
0: timer interrupt disabled
1: timer interrupt enabled (default)
Reserved bit, do not modify, and ignore on read
Prescale bits:
4
3:2
RESERVED
TimerPre
00
R/W
00: no prescale, clock is divided by 1 (default)
01: 4 stages of prescale, clock is divided by 16
10: 8 stages of prescale, clock is divided by 256
11: undefined, do not use
1
0
Timer Size
0
0
R/W
R/W
Selects 16/32 bit counter operation
0: 16 bit counter (default)
1: 32 bit counter
Selects one-shot or wrapping counter mode
0: wrapping mode (default)
OneShotCount
1: one-shot mode
Interrupt clear register, Timer1IntClr, Timer2IntClr
Any write to this register will clear the interrupt output from the counter
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