AS3525-A/-B C22O22
Data Sheet, Confidential
Ball Nr.
Ball Name
PAD Type
I/O
Ball Description
NAND FLASH chip enable
BGA224
naf_ce0_n
O
ide_cs0_n
O
IDE chip select 0
used by the host to select command block registers in the
device
E15
H11
D IO ST LSR
naf_ce1_n
ide_cs1_n
O
O
NAND FLASH chip enable
IDE chip select 1
used by the host to select control block registers in the
D IO ST LSR
device
naf_ce2_n
ide_hiown
naf_ce3_n
ide_hiorn
naf_we_n
ide_dackn
O
O
O
O
O
O
NAND FLASH chip enable
J11
D IO ST LSR
D IO ST LSR
IDE host IO write strobe
NAND FLASH chip enable
IDE host IO read strobe
NAND FLASH write enable not
G13
G14
D IO ST LSR
IDE DMA acknowledge
used by the host to initiate DMA data transfers
NAND FLASH read enable not
naf_re_n
O
I
H12
F15
D IO ST LSR
D IO ST LSR
ide_npcblid
naf_bsy_n
ide_nscblid
ide_ha[0]
ide_ha[1]
ide_ha[2]
IDE primary channel cable ID detect
NAND FLASH ready / busy not
IDE secondary channel cable ID select
IDE host address
I
I
A12
H10
D12
O
O
O
O
D OUT LSR
D OUT LSR
D OUT LSR
IDE host address
IDE host address
IDE reset not,
used by the host to reset the device
G10
ide_reset_n
D OUT LSR
I2S Output
IS2 data output
i2so_sdata
SDI
D OUT LSR
DI
O
I
M6
N6
N5
M5
data output from digital core to audio sub system, SDI and
i2so_sdata are connected on the BGA
I2S serial clock
clock output from digital core to audio sub system, SCLK and
isoi_sclk are connected on the BGA
I2S left/right clock
clock output from digital core to audio sub system, LRCK and
i2so_lrck are connected on the BGA
I2S master clock
clock output from digital core to audio sub system, MCLK and
i2so_mclk are connected on the BGA
i2so_sclk
SCLK
D OUT LSR
DI
O
I
i2so_lrck
LRCK
D OUT LSR
DI
O
I
i2so_mclk
MCLK
D OUT LSR
DI
O
I
I2S Input
I2S data input
i2si_sdata
SDO
D IN ST
DO
I
O
M7
E3
data output from audio sub system to digital core, SDO and
i2si_sdata are connected on the BGA
I2S master serial clock
serial clock output for external ADC if AS3525 is I2S master
I2S slave serial clock
serial clock input for external ADC if AS3525 is I2S slave
I2S master, left/right clock
left/right clock output for external ADC if AS3525 is I2S
master
O
I
i2si_sclk_out
D IO ST LSR
D IO ST LSR
i2si_sclk_in
O
i2si_lrck_out
D1
I
I2S slave, left/right clock
left/right clock input for external ADC if AS3525 is I2S master
I2S master, master clock
i2si_lrck_in
i2si_mclk
E4
C1
O
I
D OUT LSR
D IN ST PD
I2S data input
data input from external audio ADC
i2si_sdata_in
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