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A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
 浏览型号A3525BC21O22TRA的Datasheet PDF文件第174页浏览型号A3525BC21O22TRA的Datasheet PDF文件第175页浏览型号A3525BC21O22TRA的Datasheet PDF文件第176页浏览型号A3525BC21O22TRA的Datasheet PDF文件第177页浏览型号A3525BC21O22TRA的Datasheet PDF文件第179页浏览型号A3525BC21O22TRA的Datasheet PDF文件第180页浏览型号A3525BC21O22TRA的Datasheet PDF文件第181页浏览型号A3525BC21O22TRA的Datasheet PDF文件第182页  
AS3525-A/-B C22O22  
Data Sheet, Confidential  
Ball Nr.  
Ball Name  
PAD Type  
I/O  
Ball Description  
BGA224  
I
SPDIF data input  
data input for SPDIF to I2S conversion  
spdif_data_in  
Audio Subsystem IRQ  
INTRQ  
intrq  
DO  
D IN ST  
O
I
used by the audio/PMU subsystem to interrupt the digital  
core, INTRQ and intrq are connected on the BGA  
N1  
JTAG Debugging IF  
C2  
A1  
B2  
B1  
D3  
jtag_trst_n  
jtag_tms  
jtag_tck  
jtag_tdi  
D IN ST PD  
I
JTAG reset not  
JTAG mode select  
JTAG clock  
D IN ST PU  
I
D IN ST PU  
I
D IN ST PU  
I
JTAG data input  
JTAG data output  
jtag_tdo  
D IO ST PU LSR  
O
External Memory IF  
D OUT LSR LV  
G5  
B5  
L4  
mpmc_addr[0]  
mpmc_addr[1]  
mpmc_addr[2]  
mpmc_addr[3]  
mpmc_addr[4]  
mpmc_addr[5]  
mpmc_addr[6]  
mpmc_addr[7]  
mpmc_addr[8]  
mpmc_addr[9]  
mpmc_addr[10]  
mpmc_addr[11]  
mpmc_addr[12]  
mpmc_addr[13]  
mpmc_addr[14]  
mpmc_addr[15]  
mpmc_addr[16]  
mpmc_addr[17]  
mpmc_addr[18]  
mpmc_addr[19]  
mpmc_addr[20]  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
EXT. MEMORY address line  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
A5  
K5  
D6  
F6  
C6  
E6  
A6  
H5  
B6  
J5  
D7  
E7  
C7  
F7  
A7  
G6  
B7  
H6  
EXT. MEMORY clock enable0  
used for SDRAM devices only  
EXT. MEMORY clock enable 1  
used for SDRAM devices only  
EXT. MEMORY clock 0  
used for SDRAM devices only  
EXT. MEMORY clock 1  
used for SDRAM devices only  
EXT. MEMORY feedback clock  
used for SDRAM devices only  
EXT. MEMORY data mask 0  
used for SDRAM devices and static memories  
EXT. MEMORY data mask 1  
used for SDRAM devices and static memories  
EXT. MEMORY column address strobe not  
used for SDRAM devices only  
EXT. MEMORY dynamic memory chip select 0 not  
F8  
J6  
mpmc_cke[0]  
mpmc_cke[1]  
mpmc_clk[0]  
mpmc_clk[1]  
mpmc_fbclkin  
mpmc_dqm[0]  
mpmc_dqm[1]  
mpmc_cas_n  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D IO ST PD LSR LV  
D OUT LSR LV  
D OUT LSR LV  
D OUT LSR LV  
O
O
O
O
O
O
O
O
E8  
G7  
L5  
D8  
L6  
A8  
K6  
mpmc_dycs_n[0] D OUT LSR LV  
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.  
www.austriamicrosystems.com Revision 1.13  
178 - 194  
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