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A3525BC21O22TRA 参数 Datasheet PDF下载

A3525BC21O22TRA图片预览
型号: A3525BC21O22TRA
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的音频处理器系统 [Advanced Audio Processor System]
分类和应用:
文件页数/大小: 194 页 / 3286 K
品牌: AMSCO [ AMS(艾迈斯) ]
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AS3525-A/-B C22O22  
Data Sheet, Confidential  
Ball Nr.  
Ball Name  
PAD Type  
I/O  
Ball Description  
BGA224  
Port A  
B4  
G4  
A4  
H4  
D5  
J4  
xpa[0]  
xpa[1]  
xpa[2]  
xpa[3]  
xpa[4]  
xpa[5]  
xpa[6]  
xpa[7]  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
D IO ST PD LSR  
IO GPIO IO, Port A  
IO GPIO IO, Port A  
IO GPIO IO, Port A  
IO GPIO IO, Port A  
IO GPIO IO, Port A  
IO GPIO IO, Port A  
IO GPIO IO, Port A  
IO GPIO IO, Port A  
C5  
F5  
Port B / DISPLAY / UART  
IO GPIO IO, Port B  
xpb[0]  
I
static memory chip memory width setting for boot loader  
mpmc_stcs1mw[0  
]*  
0: 8 bit data bus  
1: 16 bit data bus  
The value is latched at reset.  
DISPLAY control output  
L10  
L11  
D IO ST PD LSR  
O
dbop_c0  
xpb[1]  
IO GPIO IO, Port B  
I
static memory chip select polarity setting for boot loader  
0: active LOW chip select  
1: active high chip select  
D IO ST PD LSR  
mpmc_stcs1pol*  
The value is latched at reset.  
DISPLAY control output  
O
dbop_c1  
xpb[2]  
IO GPIO IO, Port B  
I
static memory byte lane polarity setting for boot loader  
0: HIGH for reads, LOW for writes, used for we_n access  
1: LOW for reads, LOW for writes, used for upper and lower  
byte access  
K11  
K10  
D IO ST PD LSR  
mpmc_stcs1pb*  
The value is latched at reset.  
DISPLAY control output  
O
dbop_c2  
xpb[3]  
IO GPIO IO, Port B  
I
test mode configuration (for testing purpose only !!!)  
The value is latched at reset.  
D IO ST PD LSR  
mpmc_rel1config*  
O
DISPLAY control output  
dbop_c3  
xpb[4]  
IO GPIO IO, Port B  
K9  
D IO ST PD LSR  
D IO ST PD LSR  
IO DISPLAY data input/output (high byte)  
IO GPIO IO, Port B  
dbop_d[8]  
xpb[5]  
K12  
IO DISPLAY data input/output (high byte)  
IO GPIO IO, Port B  
dbop_d[9]  
xpb[6]  
I
UART receive line  
L12  
K13  
D IO ST PU LSR  
D IO ST PU LSR  
uart_rxd  
dbop_d[10]  
xpb[7]  
IO DISPLAY data input/output (high byte)  
IO GPIO IO, Port B  
O
UART transmit line  
uart_txd  
dbop_d[11]  
IO DISPLAY data input/output (high byte)  
Port C / DISPLAY / 2-WIRE SERIAL  
xpc[0]  
IO GPIO IO, Port C  
I
BOOT LOADER source select input  
1: internal ROM  
E5  
C4  
D IO ST PD LSR  
D IO ST PD LSR  
IntBootSel*  
0: external ROM/Flash  
IO DISPLAY data input/output (low byte)  
IO GPIO IO, Port C  
dbop_d[0]  
xpc[1]  
© 2005-2009, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.  
www.austriamicrosystems.com Revision 1.13  
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