AS3525-A/-B C22O22
Data Sheet, Confidential
8.2.2 CTBGA224 Package Ball-out
Figure 62 AS3525A Package Ball--out
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
jtag_tms
xpc_7
xpc_3
xpa_2
mpmc_addr_3 mpmc_addr_9 mpmc_addr_17 mpmc_cas_n mpmc_bls_n_0 mpmc_data_5 mpmc_data_13
ide_ha_0
naf_d_1
dbop_d14
vdd_peri
A
B
C
D
E
F
jtag_tdi
i2si_sdata_in
i2si_lrck_out
clk_ext
jtag_tck
jtag_trst_n
tmsel
xpc_5
xpc_6
xpa_0
xpc_1
xpc_4
i2si_mclk
xpc_2
xpa_1
xpa_3
xpa_5
nc
mpmc_addr_1 mpmc_addr_11 mpmc_addr_19 vss_mem
vdd_mem
vdd_mem
mpmc_data_7 mpmc_data_15
naf_d_7
naf_d_5
ide_ha_2
naf_d_9
naf_d_12
naf_wp_n
naf_re_n
xpd_1
naf_d_4
naf_d_0
naf_d_3
naf_d_13
naf_ale
naf_ce3_n
xpd_0
naf_d_2
naf_d_8
naf_d_14
naf_d_15
naf_cle
vss_peri
dbop_d15
naf_d_11
naf_ce0_n
naf_bsy_n
xpd_3
xpa_6
xpa_4
xpc_0
xpa_7
mpmc_addr_7 mpmc_addr_15 vss_mem
mpmc_data_9
ssp_fssout
ssp_rxd
jtag_tdo
mpmc_addr_5 mpmc_addr_13 mpmc_dqm_0 mpmc_stcs_n_0 mpmc_oe_n
clk_sel
i2si_sclk_out
VBUS
mpmc_addr_8 mpmc_addr_14 mpmc_clk_0 mpmc_dycs_n_1 mpmc_data_1 mpmc_data_11
id_dig
usb_vdda33t
usb_vssa33t
usb_vssa33t
mpmc_addr_6 mpmc_addr_16 mpmc_cke_0 mpmc_we_n mpmc_data_3
naf_d_10
naf_d_6
naf_ce1_n
naf_ce2_n
xpb_2
usb_dp
dbop_d12
dbop_d13
mpmc_addr_0 mpmc_addr_18 mpmc_clk_1 mpmc_data_10 mpmc_data_12 ide_reset_n
naf_we_n
xpd_4
G
H
J
usb_dm
mpmc_addr_10 mpmc_addr_20 mpmc_data_8
ssp_clkout
ide_ha_1
ssp_txd
xpb_3
xpd_7
usb_vssa33c usb_rkelvin_rext usb_vdda33c
mpmc_addr_12 mpmc_cke_1 mpmc_ras_n mpmc_data_6 mpmc_data_14
xpd_2
xpd_5
xpd_6
vdd_core
vss_core
CLK_OUT
INTRQ
nc
nc
DVDD
PwrUP
CSDA
MSUP2
LIN1R
LIN2L
mpmc_addr_4 mpmc_dycs_n_0 mpmc_bls_n_1 mpmc_data_4
xpb_4
xpb_5
xpb_7
SW_15V
CP_5V
SW_3V
VSS_3V
VSS_1V
CN_1V
K
L
mpmc_addr_2 mpmc_fbclkin mpmc_dqm_1 mpmc_stcs_n_1 mpmc_data_0 mpmc_data_2
xpb_0
xpb_1
xpb_6
CN_5V
VBAT_1V
HPL
XRES
CSCL
LOUTR
MIC2_N
LIN1L
MCLK
LRCK
SDI
SDO
LOUTL
BVSS
AVSS
VREF
AVDD
AGND
BVSS
HPCM
HPGND
BVDD
BATTEMP
HPR
ISINK
VSS_15V
BVSS2
IOVDD
QLDO2
M
N
P
R
P_PVDD
LIN2R
SCLK
BGND
CHG_IN
CHG_OUT
XOUT_32k
DVSS
MIC1_N
MIC2_P
MSUP1
MIC1_P
BVDD
BVDD
RVDD
CP_1V
XIN_24M
XOUT_24M
LSPR
LSPL
UVDD
PVDD
XIN_32k
CVDD
Note:
PINs K2, L2 and K4 are reserved for production test purposes and must be left not connected for normal operation mode.
8.2.3 CTBGA224 Ball List
Table 161 CTBGA224 Ball List
Ball Nr.
Ball Name
PAD Type
I/O
Ball Description
BGA224
XRES
DO
D IN ST
DO
D IN ST
D IN ST PD
O
I
O
I
I
XRES is generated by the PMU subsystem and connected
to reset input (active low) on the BGA
CLK_OUT is output of 20-24MHz crystal oscillator clock
and connected to clk_int on the BGA
M2
resetext_n
CLK_OUT
clk_int
M1
E1
clk_ext
external clock input (10-26MHz)
I
clock select
E2
clk_sel
D IN ST PD
0 (low): clock from internal oscillator is used
1 (high): clock from pad clk_ext is used
test mode select
For testing purpose only, has to be set to “0”.
USB mini receptacle identifier
Has to be connected to USB jack ID pin.
I
I
D2
F1
tmsel
D IN ST PD
id_dig
D IN ST (PU)
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AMSCO [ AMS(艾迈斯) ]
