AS3525-A/-B C22O22
Data Sheet, Confidential
7.3.15.4 Additional Chip Control Unit Registers
Table 93 System Configuration Register
Name
Base
AS3525_CCU_BASE
System Configuration Register
This read/write register controls system parameters.
Default
0x00
CCU_SCON
Offset: 0x0010h
Bit
Bit Name
Default
Access
Bit Description
AHB master’s priority configuration:
0: Configuration A (default)
0
priority_config
0
R/W
Highest priority: TIC (Test Interface Controller)
production test only
–
–
for
for
2nd highest priority: ARM922T
3rd highest priority: DMA
4th highest priority: USB
lowest priority: IDE
1: Configuration B
Highest priority: TIC (Test Interface Controller)
production test only
2nd highest priority: DMA
3rd highest priority: USB
4th highest priority: IDE
lowest priority: ARM922T
Table 94 Chip Version Register
Name
Base
AS3525_CCU_BASE
Chip Version Register
Version information can be read from this register.
Default
0x09
CCU_VERS
Offset: 0x0014h
Bit
Bit Name
Default
Access
Bit Description
31:12 main_version_id(19 0x2
:0)
R
main version ID
sub version ID
11:0
sub_version_id(11:
0)
0x1
R
Table 95 Spare Register 1
Name
CCU_SPARE1
Base
Default
0x00
AS3525_CCU_BASE
Metal ECO Spare Register
This register implements 32bit spare FF’s. Use for metal ECO redesign.
Offset: 0x0018h
Bit Name
Bit
Defau Access
lt
Bit Description
31:9
8
7
6
5
4
3:2
1:0
spare
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
spare bits to be used for metal ECO redesign if SET
disableDMA single request of SSPRX module if SET
disable DMA single request of SSPTX module if SET
disable DMA single request of DBOP module if SET
disable DMA single request of I2Sin module if SET
disable DMA single request of I2Sout module if SET
spare bits to be used for metal ECO redesign if SET
dma_sreq_SSPRX_off
dma_sreq_SSPTX_off
dma_sreq_DBOP_off
dma_sreq_I2Sin_off
dma_sreq_I2Sout_off
spare
mpmc_clk_inv
spare bits used to invert output clocks mpmc_clk(1:0) if SET
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