A67P16181/A67P06361 Series
Truth Table (Notes 5 - 7)
Address
Used
CE2 ZZ ADV/ R/
LD
OE
X
X
X
X
L
CLK
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
L→H
X
I/O
High-Z
High-Z
High-Z
High-Z
Q
Notes
CE
H
X
X
X
L
CE2
X
H
X
X
L
W
BWx
X
CEN
L
Operation
Deselected Cycle,
Power-down
None
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
X
Deselected Cycle,
Power-down
None
None
L
X
X
X
H
X
H
X
L
X
L
Deselected Cycle,
Power-down
L
X
L
Continue Deselect
Cycle
None
X
H
X
H
X
H
X
H
X
X
X
H
L
X
L
1
READ Cycle
(Begin Burst)
External
Next
X
L
READ Cycle
X
L
X
L
H
L
X
L
L
Q
1,7
2
(Continue Burst)
NOP/Dummy READ
(Begin Burst)
External
Next
X
H
H
X
X
X
X
X
X
L
High-Z
High-Z
D
Dummy READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
X
L
X
L
H
L
X
L
1,2,7
3
External
Next
L
L
WRITE Cycle
(Continue Burst)
NOP/WRITE Abort
(Begin Burst)
X
L
X
L
H
L
X
L
L
L
D
1,3,7
2,3
None
H
H
X
L
High-Z
WRITE Abort
(Continue Burst)
IGNORE Clock Edge
(Stall)
Next
X
X
X
X
X
X
H
X
X
X
X
X
L
High-Z 1,2,3,7
Current
None
H
X
-
4
SLEEP Mode
X
High-Z
Notes:
1. Continue Burst cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial Begin Burst cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is
executed first.
2. Dummy READ and WRITE Abort cycles can be considered NOPs because the device performs no operation. A WRITE
Abort means a WRITE command is given, but no operation is performed.
3. OE may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off the
output drivers during a WRITE cycle. Some users may use OE when the bus turn-on and turn-off times do not meet their
requirements.
4. If an Ignore Clock Edge command occurs during a READ operation, the I/O bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the Ignored Clock
Edge cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
= H means all byte write signals (
,
,
BWx
BW1 BW2
BW3
and
) are HIGH.
BWx
= L means one or more byte write signals are LOW.
BW4
6.
enables WRITEs to Byte “a” (I/Oa pins);
BW1
enables WRITEs to Byte “b” (I/Ob pins);
BW3
enables WRITEs to
BW2
Byte “c” (I/Oc pins);
enables WRITEs to Byte “d” (I/Od pins).
BW4
7. The address counter is incremented for all Continue Burst cycles.
PRELIMINARY
(August, 2004, Version 0.1)
8
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
