A67P16181/A67P06361 Series
Pin Description
Pin No.
Symbol
Description
LQFP (X18)
LQFP (X36)
37
36
37
36
A0
A1
A2 – A9
Synchronous Address Inputs : These inputs are registered
and must meet the setup and hold times around the rising
edge of CLK. Pins 83 and 84 are reserved as address bits
for higher-density 9Mb and 18Mb DBA SRAMs, respectively.
A0 and A1 are the two lest significant bits (LSB) of the
address field and set the internal burst counter if burst is
desired.
35,34,33,32,
100,99,82,81
44,45,46,47,
48,49,50,83,84
43
35,34,33,32,
100,99,82,81
45,46,47,48,
49,50,83,84,43
A11-A19
A20
A10
80
44
93 (
94 (
)
)
93 (
94 (
95 (
)
)
)
Synchronous Byte Write Enables : These active low inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on
BW1
BW1
BW2
BW3
BW1
BW2
BW3
BW2
96 (
)
BW4
BW4
the same cycle as the address,
are associated with
BWs
addresses and apply to subsequent data.
controls I/Oa
BW1
pins;
BW4
controls I/Ob pins;
BW3
controls I/Oc pins;
BW2
controls I/Od pins.
89
89
Clock : This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising edge.
All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
CLK
98
92
98
92
CE
Synchronous Chip Enable : This active low input is used to
enable the device. This input is sampled only when a new
external address is loaded (ADV/
LOW).
LD
CE2
Synchronous Chip Enable : This active low input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/ LOW). This input can be used
LD
for memory depth expansion.
97
97
CE2
OE
Synchronous Chip Enable : This active high input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/ LOW). This input can be used
LD
for memory depth expansion.
86
85
86
85
Output Enable : This active low asynchronous input enables
the data I/O output drivers.
ADV/
Synchronous Address Advance/Load : When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is loaded.
LD
When HIGH, R/ is ignored. A LOW on this pin permits a
W
new address to be loaded at CLK rising edge.
87
87
CEN
Synchronous Clock Enable : This active low input permits
CLK to propagate throughout the device. When HIGH, the
device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup
and hold times around the rising edge of CLK.
PRELIMINARY
(August, 2004, Version 0.1)
6
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
