A67P16181/A67P06361 Series
AC Characteristics (Note 4)
(0°C ≤ TA ≤ 70°C, VCC = +2.5V± 5%)
-6.5
-7.5
-8.5
Symbol
Parameter
Unit
Note
Min.
Max.
Min.
Max.
Min.
Max.
Clock
tKHKH
tKF
Clock cycle time
7.5
-
-
-8.5
-
-
10
-
-
ns
MHz
ns
Clock frequency
Clock HIGH time
Clock LOW time
133
117
100
tKHKL
tKLKH
2.5
2.5
-
-
2.8
2.8
-
-
3.0
3.0
-
-
ns
Output Times
tKHQV
tKHQX
tKHQX1
tKHQZ
tGLQV
tGLQX
tGHQZ
Clock to output valid
-
3.0
2.5
1.5
-
6.5
-
-
3.0
2.5
1.5
-
7.5
-
-
3.0
2.5
1.5
-
8.5
-
ns
ns
ns
ns
ns
ns
ns
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE to output valid
-
-
-
1,2,3
1,2,3
4
3.8
3.5
-
4.0
3.5
-
5.0
4.0
-
0
0
0
1,2,3
1,2,3
OE to output in Low-Z
OE to output in High-Z
-
3.5
-
3.5
-
4.0
Setup Times
tAVKH
tEVKH
Address
Clock enable (
1.5
1.5
1.5
1.5
-
-
-
-
2.0
2.0
2.0
2.0
-
-
-
-
2.0
2.0
2.0
2.0
-
-
-
-
ns
ns
ns
ns
5
5
5
5
)
)
CEN
tCVKH
Control signals
Data-in
tDVKH
Hold Times
tKHAX
Address
0.5
0.5
0.5
0.5
-
-
-
-
0.5
0.5
0.5
0.5
-
-
-
-
0.5
0.5
0.5
0.5
-
-
-
-
ns
ns
ns
ns
5
5
5
5
Clock enable (
tKHEX
CEN
tKHCX
Control signals
Data-in
tKHDX
Notes: 1. This parameter is sampled.
2. Output loading is specified with C1=5pF as in Figure 2.
3. Transition is measured ±200mV from steady state voltage.
4. OE can be considered a “Don’t Care” during WRITE; however, controlling OE can help fine-tune a system for
turnaround timing.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of
CLK when ADV/
is LOW and chip enabled. All other synchronous inputs meet the setup and hold times with
LD
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK (when ADV/ is LOW) to remain enabled.
LD
PRELIMINARY
(August, 2004, Version 0.1)
12
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
