A67P16181/A67P06361 Series
Pin Description (continued)
Pin No.
Symbol
Description
LQFP (X18)
LQFP (X36)
64
64
ZZ
Snooze Enable : This active high asynchronous input causes
the device to enter a low-power standby mode in which all
data in the memory array is retained. When active, all other
inputs are ignored.
88
88
R/
Read/Write : This active input determines the cycle type
W
when ADV/
is LOW. This is the only means for
LD
determining READs and WRITEs. READ cycles may not be
converted into WRITEs (and vice versa) other than by
loading a new address. A LOW on this pin permits BYTE
WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus width WRITEs occur
if all byte write enables are LOW.
52, 53, 56, 57,
58, 59, 62, 63, 51
68, 69, 72, 73, 74,
75, 78, 79, 80
2, 3, 6, 7, 8, 9, 12,
13,1
I/Oa
I/Ob
I/Oc
I/Od
SRAM Data I/O : Byte “a” is I/Oa pins; Byte “b” is I/Ob pins;
Byte “c” is I/Oc pins; Byte “d” is I/Od pins. Input data must
meet setup and hold times around CLK rising edge.
74, 73, 72, 69, 68
63, 62, 59, 58
24, 23, 22, 19, 18
13, 12, 9, 8
18, 19, 22, 23, 24,
25, 28, 29, 30
31
31
MODE
Mode: This input selects the burst sequence. A LOW on this
pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating.
1, 2, 3, 6, 7, 25, 28,
29, 30, 38, 39, 42,
51, 52, 53, 56, 57,
75, 78, 79, 95, 96
38,39,42
NC
No Connect : These pins can be left floating or connected to
GND to minimize thermal impedance.
15, 16, 41, 65, 91
15, 16, 41, 65, 91
VCC
Power Supply
4, 11, 20, 27,
54, 61, 70, 77
4, 11, 20, 27,
54, 61, 70, 77
VCCQ
Isolated Output Buffer Supply
14, 17, 40, 66, 90
14, 17, 40, 66, 90
VSS
Ground : GND.
5,10,21,26,
55,60,71,76
5,10,21,26,
55,60,71,76
VSSQ
Isolated Output Buffer Ground
PRELIMINARY
(August, 2004, Version 0.1)
7
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
