A67P16181/A67P06361 Series
Preliminary
2M X 18, 1M X 36 LVTTL, Flow-through ZeBLTM SRAM
Features
ꢀFast access time: 6.5/7.5/8.5 ns
ꢀ Clock-controlled and registered address, data and
(153, 133, 117 MHz)
control signals
ꢀZero Bus Latency between READ and WRITE cycles
allows 100% bus utilization
ꢀSignal +2.5V ± 5% power supply
ꢀIndividual Byte Write control capability
ꢀ Registered output for pipelined applications
ꢀThree separate chip enables allow wide range of options
for CE control, address pipelining
ꢀInternally self-timed write cycle
ꢀSelectable BURST mode (Linear or Interleaved)
ꢀSLEEP mode (ZZ pin) provided
ꢀAvailable in 100 pin LQFP package
ꢀClock enable (
) pin to enable clock and suspend
CEN
operations
General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family
employs high-speed, low-power CMOS designs using an
advanced CMOS process.
The A67P16181, A67P06361 SRAMs integrate a 2M X 18,
1M X 36 SRAM core with advanced synchronous peripheral
circuitry and a 2-bit burst counter. These SRAMs are
optimized for 100 percent bus utilization without the
insertion of any wait cycles during Write-Read alternation.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. The synchronous inputs include all address, all
generated by the chip and controlled by the same input pin
ADV/
in High state.
LD
Write cycles are internally self-time and synchronous with
the rising edge of the clock input and when R/ is Low.
W
The feature simplified the write interface. Individual Byte
enables allow individual bytes to be written. controls
BW1
controls I/Oc pins;
I/Oa pins;
controls I/Ob pins;
BW3
BW2
and
controls I/Od pins. Cycle types can only be
BW4
defined when an address is loaded.
The SRAM operates from a +2.5V power supply, and all
inputs and outputs are LVTTL-compatible. The device is
ideally suited for high bandwidth utilization systems.
data inputs, active low chip enable (
), two additional chip
CE
enables for easy depth expansion (CE2,
), cycle start
CE2
input (ADV/
), synchronous clock enable (
), byte
LD
CEN
write enables (
,
,
,
BW4
BW3
) and read/write
BW1 BW2
(R/ ).
W
Asynchronous inputs include the output enable (
), clock
OE
(CLK), SLEEP mode (ZZ, tied LOW if unused) and burst
mode (MODE). Burst Mode can provide either interleaved
or linear operation, burst operation can be initiated by
synchronous address Advance/Load (ADV/
) pin in Low
LD
state. Subsequent burst address can be internally
PRELIMINARY (August, 2004, Version 0.1)
2
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
