A25LQ080 Series
Quad Input Fast Program (QIFP)
The Quad Input Fast Program (QIFP) instruction is very
similar to the Page Program (PP) instruction, except that the
data are entered on four pins (IO3, IO2, IO1, IO0) instead of
only one. Inputting the data on four pins instead of one
quadruples the data transfer bandwidth compared to the
Page Program (PP) instruction. To use Quad Input Fast
Program the Quad Enable bit (QE) of Status Register-2 must
be set.
page. If less than 256 data bytes are sent to device, they are
correctly programmed at the requested addresses without
having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Quad
Input Fast Program (QIFP) instruction to program all
consecutive targeted bytes in a single sequence rather to
using several Quad Input Fast Program (QIFP) sequences
each containing only a few bytes.
The Quad Input Fast Program (QIFP) instruction is entered
S
Chip Select ( ) must be driven High after the eighth bit of
S
by driving Chip Select ( ) Low, followed by the instruction
the last data byte has been latched in, otherwise the Quad
Input Fast Program (QIFP) instruction is not executed.
code, three address bytes and at least one data byte on Data
Input Output (IO3, IO2, IO1, IO0).
If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current
page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0)
S
As soon as Chip Select ( ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Quad Input Fast Program (QIFP) cycle is in progress, the
Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
S
are all zero). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 18.
If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same
A Quad Input Fast Program (QIFP) instruction applied to a
page that is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, BP0) bits (see Table 1) is not executed.
Figure 18. Quad Input Fast Program (QIFP) instruction sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (32h)
24-Bit Address
21
Byte 1 Byte 2 Byte 3 Byte 4
23
2
1
0
22
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
IO0
IO1
IO2
MSB
IO3
7
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Byte 5 Byte 6 Byte 7 Byte 8 Byte 9 Byte 10Byte 11 Byte 12
C
Byte 253Byte 254Byte 255 Byte 256
IO0
IO1
IO2
IO3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
1
2
3
4
5
6
7
4
5
6
7
4
5
6
7
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080
(April, 2016, Version 1.0)
28
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
