A25LQ080 Series
Dual Input Fast Program (DIFP)
The Dual Input Fast Program (DIFP) instruction is very
similar to the Page Program (PP) instruction, except that the
data are entered on two pins IO0 and IO1 instead of only one.
Inputting the data on two pins instead of one doubles the
data transfer bandwidth compared to the Page Program (PP)
instruction.
correctly programmed at the requested addresses without
having any effects on the other bytes in the same page.
For optimized timings, it is recommended to use the Dual
Input Fast Program (DIFP) instruction to program all
consecutive targeted bytes in a single sequence rather to
using several Dual Input Fast Program (DIFP) sequences
each containing only a few bytes.
The Dual Input Fast Program (DIFP) instruction is entered by
S
S
driving Chip Select ( ) Low, followed by the instruction code,
Chip Select ( ) must be driven High after the eighth bit of
three address bytes and at least one data byte on Serial
Data Output (IO0 and IO1).
the last data byte has been latched in, otherwise the Dual
Input Fast Program (DIFP) instruction is not executed.
If the 8 least significant address bits (A7-A0) are not all zero,
all transmitted data that goes beyond the end of the current
page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0)
S
As soon as Chip Select ( ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Dual Input Fast Program (DIFP) cycle is in progress, the
Status Register may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Page Program cycle, and 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Dual Input Fast Program (DIFP) instruction applied to a
page that is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, BP0) bits (see Table 1) is not executed.
S
are all zero). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
If more than 256 bytes are sent to the device, previously
latched data are discarded and the last 256 data bytes are
guaranteed to be programmed correctly within the same
page. If less than 256 data bytes are sent to device, they are
Figure 17. Dual Input Fast Program (DIFP) instruction sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
IO0
IO1
Instruction (A2h)
24-Bit Address
21 1
23
2
22
3
0
MSB
High Impedance
S
C
32 33 34 35 36 37 38 39 40
41 42 43 44 45 46 47
6
7
4
2
0
1
6
7
4
0
1
6
7
4
2
0
1
6
7
4
2
0
1
6
4
2
0
1
6
7
4
2
0
1
2
IO0
Data In 1
Data In 2
Data In 3
Data In 4
Data In 5
Data In 256
5
3
5
5
3
5
3
7
5
3
5
3
IO1
3
MSB
MSB
MSB
MSB
MSB
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
27
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
