A25LQ080 Series
Chip Erase (CE)
The Chip Erase (CE) instruction sets all bits to 1 (FFh). Before
it can be accepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
code has been latched in, otherwise the Chip Erase
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Chip Erase cycle (whose duration
is tCE) is initiated. While the Chip Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Chip Erase cycle, and is 0 when it is
completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Chip Erase (CE) instruction is ignored if one, or more,
sectors/blocks are protected.
The Chip Erase (CE) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code on Serial
S
Data Input (DI). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 21. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
Figure 21. Chip Erase (CE) Instruction Sequence
S
0
1
3
2
4
5
6
7
C
Instruction
(C7h or 60h)
DI
(April, 2016, Version 1.0)
31
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