A25LQ080 Series
Program OTP (POTP)
The Program OTP instruction (POTP) is used to program at
most 64 bytes to the OTP memory area (by changing bits
from 1 to 0, only). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL) bit.
completed. At some unspecified time before the cycle is
complete, the Write Enable Latch (WEL) bit is reset.
To lock the OTP memory:
Bit 0 of the OTP control byte, that is byte 63, (see Figure 14)
is used to permanently lock the OTP memory array.
• When bit 0 of byte 63 = ’1’, the OTP memory array can be
programmed.
• When bit 0 of byte 63 = ‘0’, the OTP memory array are
read-only and cannot be programmed anymore.
Once a bit of the OTP memory has been programmed to ‘0’,
it can no longer be set to ‘1’.
The Program OTP instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code, three
address bytes and at least one data byte on Serial Data input
(DI).
S
Chip Select ( ) must be driven High after the eighth bit of
the last data byte has been latched in, otherwise the
Program OTP instruction is not executed.
The instruction sequence is shown in Figure 14.
Therefore, as soon as bit 0 of address 63h (control byte) is
set to ‘0’, the 64 bytes of the OTP memory array become
read-only in a permanent way.
Any Program OTP (POTP) instruction issued while an Erase,
Program or Write Status Register cycle is in progress is
rejected without having any effect on the cycle that is in
progress.
S
As soon as Chip Select ( ) is driven High, the self-timed
Page Program cycle (whose duration is tPP) is initiated. While
the Program OTP cycle is in progress, the Status Register
may be read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 during the
self-timed Program OTP cycle, and it is 0 when it is
Figure 14. Program OTP (POTP) instruction sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction (42h)
24-Bit Address
21
Data Byte 1
04
23
2
1
0
7
6
5
3
2
1
0
22
3
DI
MSB
MSB
S
C
41 42 43 44 45 46 47 48
40
7
49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte n
6
5
4
3
2
0
1
0
DI
5
4
1
0
5
4
1
6
3
2
6
3
2
7
7
7
MSB
MSB
MSB
Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64)
(April, 2016, Version 1.0)
24
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
