A25LQ080 Series
Block Erase (BE)
The Block Erase (BE) instruction sets to 1 (FFh) all bits inside
the chosen block. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
S
instruction is not executed. As soon as Chip Select ( ) is
driven High, the self-timed Block Erase cycle (whose duration
is tBE) is initiated. While the Block Erase cycle is in progress,
the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit
is 1 during the self-timed Block Erase cycle, and is 0 when it
is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
A Block Erase (BE) instruction applied to a page which is
protected by the Block Protect (CMP, SEC, TB, BP2, BP1,
BP0) bits (see table 1) is not executed.
The Block Erase (BE) instruction is entered by driving Chip
S
Select ( ) Low, followed by the instruction code on Serial
S
Data Input (DI). Chip Select ( ) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 20. Chip Select
S
(
) must be driven High after the eighth bit of the instruction
code has been latched in, otherwise the Block Erase
Figure 20. Block Erase (BE) Instruction Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
24-Bit Address
Instruction (D8h or 52h)
22
3
23
21
2
1
0
DI
MSB
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
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AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
