A25LQ080 Series
Read OTP (ROTP)
000000h, allowing the read sequence to be continued
indefinitely.
The Read OTP (ROTP) instruction is terminated by driving
S
The device is first selected by driving Chip Select ( ) Low.
The instruction code for the Read OTP (ROTP) instruction is
followed by a 3-byte address (A23- A0) and a dummy byte.
Each bit is latched in on the rising edge of Serial Clock (C).
Then the memory contents at that address are shifted out on
Serial Data output (DO).
S
S
Chip Select ( ) High. Chip Select ( ) can be driven High at
any time during data output. Any Read OTP (ROTP)
instruction issued while an Erase, Program or Write Status
Register cycle is in progress, is rejected without having any
effect on the cycle that is in progress.
Each bit is shifted out at the maximum frequency, fC(Max.) on
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 13.
The address is automatically incremented to the next higher
address after each byte of data is shifted out. When the
highest address is reached, the address counter rolls over to
Figure 13. Read OTP (ROTP) instruction and data-out sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
DI
Instruction
(4Bh or 48h)
24-Bit Address
21 1
23
2
22
3
0
MSB
High Impedance
DO
S
32 33 34 35 36 37 38 39 40
Dummy Byte
41 42 43 44 45 46 47
C
DI
7
6
5
4
3
2
0
1
DO
0
5
4
1
0
5
4
1
6
3
2
6
3
2
7
7
7
MSB
MSB
MSB
Data Out 1
Data Out n
Note: A23 to A6 are don’t care. (1 ≤ n ≤ 64)
(April, 2016, Version 1.0)
23
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