A25LQ080 Series
Read Data Bytes at Higher Speed by Quad Output (FAST_READ_QUAD_OUTPUT)
The FAST_READ_QUAD_OUTPUT (6Bh) instruction is
similar to the FAST_READ (0Bh) instruction except the data
is output on four pins (IO0, IO1, IO2, IO3), instead of just DO.
This allows data to be transferred from the A25LQ080 at
quadruple the rate of standard SPI devices.
This is accomplished by adding eight “dummy” clocks after
the 24-bit address as shown in figure 11. The dummy clocks
allow the device’s internal circuits additional time for setting
up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out
clock.
Similar
to
the
FAST_READ
instruction,
the
FAST_READ_QUAD_OUTPUT instruction can operate at
the highest possible frequency of fC (See AC Characteristics).
Figure 11. FAST_READ_QUAD_OUTPUT Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10
28 29 30 31
C
IO0
Instruction (6Bh)
24-Bit Address
21
23
2
1
0
22
3
MSB
High Impedance
IO1,2,3
S
C
33 34 35 36 37 38 39 40
Dummy Byte
32
7
41 42 43 44 45 46 47
IO switches from input to output
IO0
6
5
4
3
2
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
4
5
6
7
IO1
IO2
IO3
Data Out 1Data Out 2Data Out 3Data Out 4
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
21
AMIC Technology Corp.