A25LQ080 Series
Read Data Bytes at Higher Speed by Dual Output (FAST_READ_DUAL_OUTPUT)
The FAST_READ_DUAL_OUTPUT (3Bh) instruction is
similar to the FAST_READ (0Bh) instruction except the data
is output on two pins, IO0 and IO1, instead of just DO. This
allows data to be transferred from the A25LQ080 at twice the
rate of standard SPI devices.
This is accomplished by adding eight “dummy” clocks after
the 24-bit address as shown in figure 9. The dummy clocks
allow the device’s internal circuits additional time for setting
up the initial address. The input data during the dummy
clocks is “don’t care”. However, the IO0 and IO1 pins should
be high-impedance prior to the falling edge of the first data
out clock.
Similar
to
the
FAST_READ
instruction,
the
FAST_READ_DUAL_OUTPUT instruction can operate at the
highest possible frequency of fC (See AC Characteristics).
Figure 9. FAST_READ_DUAL_OUTPUT Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10
28 29 30 31
C
IO0
IO1
Instruction (3Bh)
24-Bit Address
21
23
2
1
0
22
3
MSB
High Impedance
S
C
33 34 35 36 37 38 39 40
Dummy Byte
32
7
41 42 43 44 45 46 47
DIO switches from input to output
IO0
IO1
6
5
4
3
2
0
6
4
2
0
6
4
2
0
6
4
2
3
0
1
6
7
4
5
2
3
0
1
1
3
1
3
5
7
5
1
5
7
7
7
MSB
MSB
MSB
Data Out 1
Data Out 2
Data Out 3
Data Out 4
Note: Address bits A23 to A20 are Don’t Care, for A25LQ080.
(April, 2016, Version 1.0)
19
AMIC Technology Corp.
AMICC [ AMIC TECHNOLOGY ]
