A25LQ080 Series
SUS bit. The Suspend Status (SUS) bit is a volatile read only
bit in the status register (b15) which is set to 1 after executing
a Program/Erase Suspend instruction. The SUS bit is cleared
to 0 by Program/Erase Resume instruction as well as a
power-down, power-up cycle.
Note:
1. When APT is 0, BP2, BP1, BP0 won’t be changed after
power-on.
2. When APT is 1 and CMP is 0, all BP2, BP1, BP0 will be
set to 1 after power-on.
3. When APT is 1 and CMP is 1, all BP2, BP1, BP0 will be
set to 0 after power-on.
Figure 5. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
6
0
1
2
3
4
5
7
8
9 10 11 12
14 15 16 17 18 19 20 21 22 23
13
C
Instruction (05h or 35h)
DI
Status Register 1 or 2 Out
Status Register 1 or 2 Out
High Impedance
DO
7
6
5
4
3
2
1
0
7
6
5
4
3
1
0
7
2
MSB
MSB
(April, 2016, Version 1.0)
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