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N64S0818HDA 参数 Datasheet PDF下载

N64S0818HDA图片预览
型号: N64S0818HDA
PDF下载: 下载PDF文件 查看货源
内容描述: 64Kb的低功耗串行SRAM的8K × 8位组织 [64Kb Low Power Serial SRAMs 8K 】 8 bit Organization]
分类和应用: 静态存储器
文件页数/大小: 15 页 / 201 K
品牌: AMI [ AMI SEMICONDUCTOR ]
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N64S0818HDA/N64S0830HDA  
Advance Information  
AMI Semiconductor, Inc.  
Control Signal Descriptions  
Signal  
Name  
I/O  
Description  
A low level selects the device and a high level puts the device in standby mode. If  
CS is brought high during a program cycle, the cycle will complete and then the  
device will enter standby mode. When CS is high, SO is in high-Z. CS must be  
driven low after power-up prior to any sequence being started.  
CS  
Chip Select  
I
Synchronizes all activities between the memory and controller. All incoming  
addresses, data and instructions are latched on the rising edge of SCK. Data out is  
updated on SO after the falling edge of SCK.  
SCK  
Serial Clock  
I
SI  
SO  
Serial Data In  
Serial Data Out  
I
O
Receives instructions, addresses and data on the rising edge of SCK.  
Data is transferred out after the falling edge of SCK.  
A high level is required for normal operation. Once the device is selected and a  
serial sequence is started, this input may be taken low to pause serial communica-  
tion without resetting the serial sequence. The pin must be brought low while SCK  
is low for immediate use. If SCK is not low, the Hold function will not be invoked  
until the next SCK high to low transition. The device must remain selected during  
this sequence. SO is high-Z during the Hold time and SI and SCK are inputs are  
ignored. To resume operations, HOLD must be pulled high while the SCK pin is  
low.  
HOLD  
Hold  
I
Lowering the HOLD input at any time will take to SO output to High-Z.  
Functional Operation  
Basic Operation  
The 64Kb serial SRAM is designed to interface directly with a standard Serial Peripheral Interface (SPI)  
common on many standard micro-controllers. It may also interface with other non-SPI ports by  
programming discrete I/O lines to operate the device.  
The serial SRAM contains an 8-bit instruction register and is accessed via the SI pin. The CS pin must be  
low and the HOLD pin must be high for the entire operation. Data is sampled on the first rising edge of  
SCK after CS goes low. If the clock line is shared, the user can assert the HOLD input and place the  
device into a Hold mode. After releasing the HOLD pin, the operation will resume from the point where it  
was held.  
The following table contains the possible instructions and formats. All instructions, addresses and data are  
transferred MSB first and LSB last.  
Instruction Set  
Instruction  
Instruction Format  
Description  
READ  
WRITE  
RDSR  
WRSR  
0000 0011  
0000 0010  
0000 0101  
0000 0001  
Read data from memory starting at selected address  
Write data to memory starting at selected address  
Read status register  
Write status register  
6
This is a developmental specification and is subject to change without notice.