欢迎访问ic37.com |
会员登录 免费注册
发布采购

N64S0818HDA 参数 Datasheet PDF下载

N64S0818HDA图片预览
型号: N64S0818HDA
PDF下载: 下载PDF文件 查看货源
内容描述: 64Kb的低功耗串行SRAM的8K × 8位组织 [64Kb Low Power Serial SRAMs 8K 】 8 bit Organization]
分类和应用: 静态存储器
文件页数/大小: 15 页 / 201 K
品牌: AMI [ AMI SEMICONDUCTOR ]
 浏览型号N64S0818HDA的Datasheet PDF文件第5页浏览型号N64S0818HDA的Datasheet PDF文件第6页浏览型号N64S0818HDA的Datasheet PDF文件第7页浏览型号N64S0818HDA的Datasheet PDF文件第8页浏览型号N64S0818HDA的Datasheet PDF文件第10页浏览型号N64S0818HDA的Datasheet PDF文件第11页浏览型号N64S0818HDA的Datasheet PDF文件第12页浏览型号N64S0818HDA的Datasheet PDF文件第13页  
N64S0818HDA/N64S0830HDA  
Advance Information  
AMI Semiconductor, Inc.  
WRITE Operations  
The serial SRAM WRITE is selected by enabling CS low. First, the 8-bit WRITE instruction is transmitted  
to the device followed by the 16-bit address with the 3 MSBs being don’t care. After the WRITE instruction  
and addresses are sent, the data to be stored in memory is shifted in on the SI pin.  
If operating in page mode, after the initial word of data is shifted in, additional data words can be written as  
long as the address requested is sequential on the same page. Simply write the data on SI pin and  
continue to provide clock pulses. The internal address pointer is automatically incremented to the next  
higher address on the page after each word of data is written in. This can be continued for the entire page  
length of 32 words long. At the end of the page, the addresses pointer will be wrapped to the 0 word  
address within the page and the operation can be continuously looped over the 32 words of the same  
page. The new data will replace data already stored in the memory locations.  
If operating in burst mode, after the initial word of data is shifted in, additional data words can be written to  
the next sequential memory locations by continuing to provide clock pulses. The internal address pointer  
is automatically incremented to the next higher address after each word of data is read out. This can be  
continued for the entire array and when the highest address is reached (1FFFh), the address counter  
wraps to the address 0000h. This allows the burst write cycle to be continued indefinitely. Again, the new  
data will replace data already stored in the memory locations.  
All WRITE operations are terminated by pulling CS high.  
Word WRITE Sequence  
CS  
SCK  
0
1
2
3
4
5
6
7
8
9
10 11  
21 22 23 24 25 26 27 28 29 30 31  
Data In  
Instruction  
16-bit address  
SI  
0
0
0
0
0
0
1
0
15 14 13 12  
2
1
0
7
6
5
4
3
2
1
0
...  
High-Z  
SO  
9
This is a developmental specification and is subject to change without notice.