Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
acknowledge the transfer but does generate a STOP condition.
5.2.5 Sequential Register Read Procedure
Sequential read operations allow the master to read from each
register in order. The register pointer is automatically
incremented by one after each read. This procedure is more
efficient than the random register read if several registers must
be read.
5.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to each
register in order. The register pointer is automatically
incremented after each write. This procedure is more efficient
than the random register write if several registers must be
written.
To perform a read procedure, the R/W bit that is transmitted
after the seven-bit address is a logic-low, as in the register
write procedure. This indicates to the addressed slave device
that a register address will follow after the slave device
acknowledges its device address. The register address is then
written into the slave's address pointer.
To initiate a write procedure, the R/W bit that is transmitted
after the seven-bit device address is a logic-low. This indicates
to the addressed slave device that a register address will follow
after the slave device acknowledges its device address. The
register address is written into the slave's address pointer.
Following an acknowledge by the slave, the master is allowed
to write up to eight bytes of data into the addressed register
before the register address pointer overflows back to the
beginning address.
Following an acknowledge by the slave, the master generates
a repeated START condition. The repeated START terminates
the write procedure, but not until after the slave's address
pointer is set. The slave address is then resent, with the R/W
bit set this time to a logic-high, indicating to the slave that data
will be read. The slave will acknowledge the device address,
and then transmits all eight bytes of data starting with the initial
addressed register. The register address pointer will overflow if
the initial register address is larger than zero. After the last byte
of data, the master does not acknowledge the transfer but
does generate a STOP condition.
An acknowledge by the device between each byte of data must
occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not wait for
the STOP condition to occur. Registers are therefore updated
at different times during a sequential register write.
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