Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
modulus. Selected moduli below 12 are also permitted.
Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not
available on date codes prior to 0108).
4.0 Functional Block Description
4.1 Phase Locked Loop (PLL)
The phase locked loop is a standard phase- and frequency-
locked loop architecture. The PLL consists of a reference
divider, a phase-frequency detector (PFD), a charge pump, an
internal loop filter, a voltage-controlled oscillator (VCO), a
feedback divider, and a post divider.
4.1.3 Post Divider
The post divider consists of three individually programmable
dividers, as shown in Figure 3.
The reference frequency (generated by either the on-board
crystal oscillator or an external frequency source), is first
reduced by the Reference Divider. The integer value that the
frequency is divided by is called the modulus and is denoted as
NR for the reference divider. This divided reference is then fed
into the PFD.
POST1[3:0]
POST2[3:0]
POST3[1:0]
Post
Divider 1
Post
Divider 2
Post
Divider 3
(NP3)
f
fCLK
VCO
(NP1
)
(NP2
)
POST DIVIDER (N
)
Px
The VCO frequency is fed back to the PFD through the
feedback divider (the modulus is denoted by NF).
Figure 3: Post Divider
The PFD will drive the VCO up or down in frequency until the
divided reference frequency and the divided VCO frequency
appearing at the inputs of the PFD are equal. The input/output
relationship between the reference frequency and the VCO
frequency is then:
P1
P2
The moduli of the individual dividers are denoted as N , N
P3
Px
and N , and together they make up the array modulus N .
NPx = NP × NP × NP
1
2
3
The post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of speeds
compared to the variety of output clock speeds that the device
is required to generate. Second, the extra integer in the
denominator permits more flexibility in the programming of the
loop for many applications where frequencies must be
achieved exactly.
fVCO
NF
fREF
NR
=
This basic PLL equation can be rewritten as
NF
NR
fVCO
= fREF
A post-divider (actually a series combination of three post
dividers) follows the PLL and the final equation for device
output frequency is:
Note that a nominal 50/50 duty factor is always preserved
(even for selections which have an odd modulus).
See Table 8 for additional information.
NF
1
fCLK = fREF
NR NPx
4.1.4 Crystal Oscillator
The FS7140 is equipped with a Pierce-type crystal oscillator.
The crystal is operated in parallel resonant mode. Internal
load capacitance is provided for the crystal. While a
recommended load capacitance for the crystal is specified,
crystals for other standard load capacitances may be used if
great precision of the reference frequency (100ppm or less) is
not required.
4.1.1 Reference Divider
The reference divider is designed for low phase jitter. The
divider accepts the output of either the crystal oscillator circuit
or an external reference frequency. The reference divider is a
12 bit divider, and can be programmed for any modulus from 1
to 4095 (divide by 1 not available on date codes prior to 0108).
4.1.5 Reference Divider Source MUX
4.1.2 Feedback Divider
The source of frequency for the reference divider can be
chosen to be the device crystal oscillator or the REF pin by the
REFDSRC bit.
The feedback divider is based on a dual-modulus divider (also
called dual-modulus prescaler) technique. It permits division
by any integer value between 12 and 16383. Simply program
the FBKDIV register with the binary equivalent of the desired
When not using the crystal oscillator, it is preferred to connect
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