Data Sheet
FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator
Table 5: Device Configuration Bits
Table 9: Post Divider Control Bits
Name
Description
Name
Description
REFerence Divider SouRCe
[0] = Crystal Oscillator / [1] = REF Pin
FeedB ack Divider SouRCe
[0] = VCO Output / [1] = Post Divider Output
SHUTdown1
[0] = Normal / [1] = Powered Down
SHUTdown2
[0] = Normal / [1] = Powered Down
CLKP/CLKN Output Mode
[0] = PECL Output / [1] CMOS Output
P1
POST Divider #1 (N ) Modulus
REFDSRC
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
1
2
3
4
5
6
7
8
9
FBKDSRC
SHUT1
SHUT2
CMOS
POST1[3:0]
10
11
12
Table 6: Main Loop Tuning Bits
Name
Description
Charge Pump Current
Do not use
[1110]
[1111]
[00]
[01]
2.0µA
4.5µA
CP[1:0]
P2
POST Divider #2 (N ) Modulus
[10]
[11]
11.0µA
22.5µA
[0000]
[0001]
[0010]
[0011]
[0100]
[0101]
[0110]
[0111]
[1000]
[1001]
[1010]
[1011]
[1100]
[1101]
[1110]
[1111]
1
2
3
4
5
6
7
8
9
Loop Filter Resistor Select
[00]
[01]
[10]
400KΩ
133KΩ
30KΩ
LR[1:0]
LC
[11]
12KΩ
Loop Filter Capacitor Select
POST2[3:0]
[0]
[1]
185pF
500pF
10
11
12
Table 7: PLL Divider Control Bits
NAME
DESCRIPTION
Do not use
R
REFerence DIVider (N )
REFDIV[11:0]
FBKDIV[13:0]
R
FeedBacK DIVider (N )
P3
POST Divider #3 (N ) Modulus
[00]
[01]
[10]
[11]
1
2
4
8
POST3[1:0]
Table 8: SYNC Control Bits (FS7145 only)
Name
Description
SYNC Enable
[0] = Disabled / [1] = Enabled
SYNC POLarity
SYNCEN
SYNCPOL
[0] = Negative Edge / [1] = Positive Edge
AMI Semiconductor - Rev. 3.0
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